Important Dates

List of Topics  

We solicit papers of original research including, but not limited to, the following areas:

• Memory Access Decoupling

• Compiler Based Decoupling

• Function Decoupling

• Processor Architecture

• Latency Tolerance

• Instruction Level Parallelism

• Thread Level Parallelism

• New RAM Architectures

• Multithreading

• Chip Multiprocessors

Most of today's advanced processor architectures are based on the Superscalar and Multiple Issue paradigm. These include MIPS-R10000, Power-PC, Ultra-Sparc, Alpha 21164 and 264, Pentium family.

Research has been developed to exploit Instruction Level Parallelism (ILP), Branch Prediction, Predicative Execution, Speculative Loads, VLIW (e.g. Itanium, i.e. IA-64/EPIC), Multithreaded Approach (Compaq EV8, i.e. Alpha 21464), and Chip Multiprocessor (CMP, IBM Power4).

This workshop aims to bring up an old idea, Access Decoupling, in this new arena. We wish to hear from people working in multithreading, Thread Level Parallelism, ILP, superscalar processors, novel RAM architectures, memory hierarchy optimizations, data dependencies optimizations both from compiler and architectural point of view.

Many research groups have recently revived Access Decoupling and its now time to show how this paradigm can wide the spectrum of solutions to overcome the memory-wall problem. In particular, we'd like to explore new sources for parallelism.

In this workshop, we wish to put in contact people interested in evaluating how the old idea of memory access decoupling could be applied in this new scenario as a viable alternative to new processor designs.

Organizing Commitee

Program Commitee (so far...)