1b) THESIS: Several thesis are available: please contact me, at my office. Some topics are posted on the Faculty Web Site. Here are acknowledgements for best recent thesis:
JCACHESIM by Christos Ververidis, an educational
visual tool in Java for performance evaluation of MIPS based systems with cache.
Ing. Ververidis' first employment: Software Engineer & Quality Support Landis+Gyr A.E. Digital Operations. He is using his great experience on the Java language. He is working 5km from home at this multinational company (490Meuro sales, 3600+ employees).
2) I'm (always) SEEKING GOOD COLLABORATORS, Research Funds, Industrial Parternship to fuel
High Performance Computer Architecture Research Projects with particular emphasis on SCALABLE ARCHITECTURES and EMBEDDED SYSTEMS.
Winner of Post-Doc Research grant at BASSNET, working on Bass-Security project.
Paolo Bennati Low-Power and Adaptive Embedded Systems. (tutor 2004-2007).
Research Doctor (PhD) April 2008.
Post-Doc at Department of Information Engineering - SIENA (2007-2008).
Zdravko Popovic Scalable Architectures for Embedded Systems (tutor 2005-2009).
Research Doctor (PhD) September 2009.
Zdravko Popovic completed a 3-month research exchange activity at the University of Cyprus, Nicosia, CY.
Zdravko Popovic completed a 3-month internship exchange activity at the Barcelona Supercomputing Center, ES.
Nikola Puzovic Scalable Architectures for High Performance Computing (tutor 2005-2009).
Resarch Associate at Barcelona Computing Center, February 2011.
Resarch Associate at University of Siena.
Research Doctor (PhD) September 2009.
Nikola Puzovic completed a 6-month internship at ST-Microelectronics (Manno, Switzerland) during his PhD studies at the University of Siena.
4a)
YEARS 2010-2013: TERAFLUX (Concurrent Teradevice Computing). Integrated Project within the 7th Framework Programme of the European Union. Coordinated by the University of Siena. (Grant Agreement 249013 - Total Budget 5.7 MILLIONS Euro)
YEARS 2010-2012: ERA (Embedded Reconfigurable Architecture). STREP Project within the 7th Framework Programme of the European Union. Participated by the University of Siena (Grant Agreement 249059 - Total Budget 2.8 MILLIONS Euro)
YEARS 2008-2012: HiPEAC-2 (High Performance Embedded-System Architecture and Compilation). Network of Excellence within the 7th Framework Programme of the European Union IST-217068. (Total Budget 4.8 MILLIONS EURO).
4b) PAST PROJECTS
YEARS 2006-2009: SARC (Scalable ARChitecutre). Integrated Project within the 6th Framework Programme of the European Union. Contract 27648. (Total BUDGET 8.5 MILLIONS EURO), in affiliation with University of Pisa.
YEARS 2004-2008: HiPEAC (High Performance Embedded-System Architecture and Compilation). Network of Excellence within the 6th Framework Programme of the European Union. Contract IST-004408 (Total Budget 3.9 MILLIONS EURO).
Program Committee Member: IEEE FPL-2012, Oslo, Norway, August 2012.
Program Committee Member: IEEE M2A2-2012 Workshop IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms, Madrid, Spain, July 2012.
Program Committee Member: IEEE ICCD-2012, Montreal, Quebec, Canada, September 2012
I investigated the performance of a
new coherence protocol (PSCR)
on Multithreaded Shared-Bus Shared-Memory Multiprocessors
I built a Workload Generation Environment named
Trace Factory.
I supported the development of
ChARM
project under Motif, a part of the JumpStart tool chain (now evolved into
JumpStartXE(TM) by NXP Semiconductors (founded by Philips))
in cooperation with VLSI Tech. Inc., which later became Philips Semiconductor and now NXP
PERSONAL INTERESTS
I love skiing, trekking, swimming. Here are some interesting sites:
