RESEARCH · TEACHING · SERVICE · SELECTED PAPERS · STUDENTS · TOOLS · THESIS · BIO · CV · LINKS

ABOUT ME

• I'm currently the Coordinator of an EU-funded 4-year project on Multicores: TERAFLUX.
• My main Research Area is COMPUTER ARCHITECTURE with emphasis on Multiprocessor/Multicore issues (processor, coherence, programmability).
• I'm an Associate Professor of Computer Engineering ("SSD ING-INF/05" in Italy) since October 1st, 2006.
• I've been an Assistant Professor ("University Researcher" in Italy) of Computer Engineering ("SSD ING-INF/05" in Italy) since March 15th, 1999.
• I've been a Post-Doc Research Associate at UAH (University of Alabama in Huntsville) working with prof. K. M. Kavi and CRASH group on Multithreaded Architectures.
• I got my Ph.D. in Computer Engineering on March 16th, 1999 from University of Pisa, Italy. Thesis title: Evaluation of a Coherence Protocol for the Elimination of Passive Sharing in Shared-Memory Multithreaded Multiprocessors. Advisor Prof. C. A. Prete.
• I graduated in Electronic Engineering in July 1995; Thesis title: Trace Driven Performance Evaluation of Multiprocessors.
• I am a member of the following Professional Societies: IEEE, IEEE Computer Society (S'89,M'00,SM'04), and ACM.
• ...and Interest Groups: IEEE TCCA, ACM SIGARCH, ACM SIGMICRO, and ACM SIGBED.
• Here is my Short Biography,  (also in Italian). Curriculum Vitae (also in Italian).
• A partial list of my papers and SELECTED PAPERS.
• My GPG public key.

WHAT AM I DOING, NOW?     (Last Updated: )

• TEACHING

  • 1a) I'm an Associate Professor of Computer Architecture: DIDATTICA
    • Assigned 5th WORLDWIDE PRIZE at IEEE Computer Design International Competition 2002:
      Team Mentor for Student Project on Bluetooth technology.
      
    
    
  • 1b) THESIS: Several thesis are available: please contact me, at my office. Some topics are posted on the Faculty Web Site. Here are acknowledgements for best recent thesis:
    • JCACHESIM by Christos Ververidis, an educational visual tool in Java for performance evaluation of MIPS based systems with cache.
      
      • Ing. Ververidis' first employment: Software Engineer & Quality Support Landis+Gyr A.E. Digital Operations. He is using his great experience on the Java language. He is working 5km from home at this multinational company (490Meuro sales, 3600+ employees).
  
  

• RESEARCH

  • 2) I'm (always) SEEKING GOOD COLLABORATORS, Research Funds, Industrial Parternship to fuel High Performance Computer Architecture Research Projects with particular emphasis on SCALABLE ARCHITECTURES and EMBEDDED SYSTEMS.
    
    
  • 3) Current and Past PhD STUDENTS:
    • Irina Branovic Architectural Support for Elliptic Curve Cryptography (ECC) (co-tutor 2002-2005).
      • Research Doctor (PhD) April 2005.
      • Designer for ARM-based Systems at Zucchetti Centro Sistemi.
      • Winner of Post-Doc Research grant at BASSNET, working on Bass-Security project.
    • Paolo Bennati Low-Power and Adaptive Embedded Systems. (tutor 2004-2007).
      • Research Doctor (PhD) April 2008.
      • Post-Doc at Department of Information Engineering - SIENA (2007-2008).
    • Zdravko Popovic Scalable Architectures for Embedded Systems (tutor 2005-2009).
      • Research Doctor (PhD) September 2009.
      • Zdravko Popovic completed a 3-month research exchange activity at the University of Cyprus, Nicosia, CY.
      • Zdravko Popovic completed a 3-month internship exchange activity at the Barcelona Supercomputing Center, ES.
    • Nikola Puzovic Scalable Architectures for High Performance Computing (tutor 2005-2009).
      • Research Doctor (PhD) September 2009.
      • Nikola Puzovic completed a 6-month internship at ST-Microelectronics (Manno, Switzerland) during his PhD studies at the University of Siena.
      
      
    • 4a) CURRENT PROJECTS (Apparently I got some funding!!)
      • YEARS 2010-2013: TERAFLUX (Concurrent Teradevice Computing). Integrated Project within the 7th Framework Programme of the European Union. Coordinated by the University of Siena. (Grant Agreement 249013 - Total Budget 5.7 MILLIONS Euro)
        
      • YEARS 2010-2012: ERA (Embedded Reconfigurable Architecture). STREP Project within the 7th Framework Programme of the European Union. Participated by the University of Siena (Grant Agreement 249059 - Total Budget 2.8 MILLIONS Euro)
        
      • YEARS 2008-2012: HiPEAC-2 (High Performance Embedded-System Architecture and Compilation). Network of Excellence within the 7th Framework Programme of the European Union IST-217068. (Total Budget 4.8 MILLIONS EURO).
        
      • YEARS 2006-2009: SARC (Scalable ARChitecutre). Integrated Project within the 6th Framework Programme of the European Union. Contract 27648. (Total BUDGET 8.5 MILLIONS EURO), in affiliation with University of Pisa.
        
      
      
    • 4b) PAST PROJECTS
      • YEARS 2008-2009: INTEGRATION OF A SIGNING ANIMATED 3-D AVATAR IN THE DIGITAL TERRESTRIAL RECEIVERS (DVB-T) FOR HELPING THE DEAF. Funded by the Fondazione Monte dei Paschi di Siena. In cooperation with Department of Communication Sciences, Associazione Italiana Educatori Sordi (AIES), Ente Nazionale Sordi (ENS), REGIONE TOSCANA and Centro Ricerche RAI RADIOTELEVISIONE ITALIANA
        
      • YEARS 2004-2008: HiPEAC (High Performance Embedded-System Architecture and Compilation). Network of Excellence within the 6th Framework Programme of the European Union. Contract IST-004408 (Total Budget 3.9 MILLIONS EURO).
        
      • YEARS 2004-2005: INNOVATIVE ARCHITECTURES FOR HIGH PERFORMANCE PROCESSORS. Funded by the Italian Ministry for the Education and the University (MIUR) as a FIRB project (special Italian Funding for Basic Research).
        
      • YEAR 2004: MULTIMEDIA DEVICE FOR HELPING THE DEAF. Funded by the Fondazione Monte dei Paschi di Siena. First Prize 2006 for Section "Social Integration" Forum Public Administration (Ministry of Innovation and Technology, CNIPA, Ericsson, ASPHI)
        
      • YEARS 2004-2005: INNOVATIVE PROCESSOR ARCHITECTURES FOR EMBEDDED MULTIMEDIA APPLICATIONS. Funded by the University of Siena.
        
        
      • 5) TOOLS that I made available to the community:
        • The BASICRYPT BENCHMARK-SUITE
        • The WEBMIPS: Web-based MIPS processor simulator
        • JCACHESIM by Christos Ververidis, cache+cpu web-based simulator.
      
      

    • SERVICE

      • 6) SOME RECENT ACTIVITY IN THE INTERNATIONAL SCIENTIFIC COMMUNITY
      • Program Committee Member: IEEE FPL-2010, Milano, Italy, August 2010
      • Program Committee Member: MULTIPROG-2010 Workshop, Pisa, Italy, January 2010
      • Program Committee Member: ACM SAC-2010 Special Track, Sierre, Switzerland, March 2010
      • Program Committee Co-Chair: HiPEAC WRC 2010, Pisa, Italy, January 2010
      • Publicity Chair: HiPEAC 2010, Pisa, Italy, January 2010
      • Program Committee Member: IEEE ICCD-2009, Lake Tahoe, California (USA), October 2009
      • Program Committee Member: WoRMES 2009, Vancouver, Canada, August 2009
      • Program Committee Member: ICPP 2009, Vienna, Austria, September 2009
      • Program Committee Member: Computing Frontiers 2009, Ischia, Italy, May 2009
      • Program Committee Member: ACM SAC-2009 Special Track, Honolulu, Hawaii (USA), March 2009
      • Program Committee Member: MULTIPROG-2009 Workshop, Paphos, Cyprus, January 2009
      • Program Committee Member: IEEE ICCD-2008, Lake Tahoe, California (USA), October 2008
      • Program Committee Member: MEDEA-2008 Workshop, Toronto, Canada, October 2008
      • Program Committee Member: IEEE SEC-2008, Beijing, China, October 2008
      • Financial/Local Co-Chair: WAIFI-2008 Workshop, Siena, Italy, July 2008
      • Program Committee Member: ACM SAC-2008 Special Track, Fortaleza, Brazil, March 2008
      • Program Committee Member: MULTIPROG-2008 Workshop, Goteborg, Sweden, January 2008
      • Program Committee Member: MEDEA-2007 Workshop, Brasov, Romania, September 2007
      • Program Committee Member: HiPEAC 2007 Conference , Ghent, Belgium, January 2007
      • Program Committee Member: ACM SAC-2007 Special Track, Seoul, Korea, March 2007
      • EU Independent Expert: Reviewer of SHAPES project, 2006-2008
      • Program Committee Member: MEDEA-2006 Workshop, Seattle, Washington, USA, September 2006
      • Program Committee Member: ACM SAC-2006 Special Track, Dijon, France, April 2006
      • Program Committee Member: HiPEAC 2005 Conference , Barcelona, Spain, November 2005
      • Program Committee Member: MEDEA-2005 Workshop, Saint Loius, Missouri, USA, September 2005
      • Program Committee Member: SCOPES-2005 Workshop, Dallas, Texas, USA, September 2005
      • Program Committee Vice-Chair: ESA-05 Conference, Las Vegas, Nevada, USA, June 2005
      • Program Committee Member: PDES-05 IEEE/IFIP Workshop, Fukuoka, Japan, July 2005
      • Deputy Steering Committee: HiPEAC Network of Excellence, 6th Framework Programme, European Union, 2004-2008
      • Program Committee Member: ACM SAC-2005 Special Track, Santa Fe, New Mexico, USA, March 2005
      • Program Committee Member: MEDEA-2004 Workshop, Antibes Juan-les-Pins, France, September 2004
      • Program Committee Member: ACM SAC-2004 Special Track, Nycosia, CIPRO, March 2004
      • Program Committee Member: MEDEA-2003 Workshop, New Orleans, Louisiana (USA), September 2003
      • Program Committee Member: ACM SAC-2003 Special Track, Melbourne, Florida (USA), March 2003
      • Program Committee Member: PACT-2002 Conference, Charlottesville, Virginia (USA), September 2002
      • Program Committee Member: MEDEA-2002 Workshop, Charlottesville, Virginia (USA), September 2002
      • IEEE Judge for IEEE-CSIDC Computer Design Competition 2001 based on Bluetooth technology. Sponsored by IEEE, Intel, Toshiba, Ericsson, AMD, Microsoft, Lucent, EMC, Hewlett-Packard, Sun, Motorola. Look here for some other pictures.
      • Program Committee Member and Organizer: MEDEA-2001 Workshop, Barcelona, Spain (EU), September 2001
      • Program Committee Member, Organizer and Promoter: MEDEA-2000 Workshop, Philadelphia, Pennsylvania (USA), October 2000
      
      
    • 7) SOME RECENT ACTIVITY IN THE FACULTY OF ENGINEERING (UNIVERSITY OF SIENA)
      • President of the Self-Evaluation Committee (RAV) for the Information Engineering Laurea (2006)
      • Member of the PhD program board ("Dottorato di Ricerca") in Information Engineering (2002-present)
      • Member of the Reference Committe ("Laurea Magistrale") in Information Engineering (2009-present)
      • Member of Admission Committee ("Laurea Magistrale") in Information Engineering (2009-present)
      • Member of the MASTER GINTS program board (2000-present)
      • Member of the MS program board ("Laurea Magistrale") in Information Engineering (2005-2009)
      • Member of the BS program board ("Laurea") in Information Engineering (2005-2009)
      • Member of the LAN Architecture Group(2001-2008)
      • Member of the Orientation Committee (2001-2005)
  
  

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  • LINKS

    • SOME PAST EXPERIENCE

      • I investigated the performance of a new coherence protocol (PSCR) on Multithreaded Shared-Bus Shared-Memory Multiprocessors
      • I built a Workload Generation Environment named Trace Factory.
      • I supported the development of ChARM project under Motif, a part of the JumpStart tool chain (now evolved into JumpStartXE(TM) by NXP Semiconductors (founded by Philips)) in cooperation with VLSI Tech. Inc., which later became Philips Semiconductor and now NXP

    • PERSONAL INTERESTS

      • I love skiing, trekking, swimming. Here are some interesting sites:
        • DOLOMITI
        • ABETONE

    • NICE PLACES I LIKE NEARBY SIENA

      • Podere Renaccio

    • HOW TO GET TO SIENA-FACULTY-OF-ENGINEERING FROM A1-EXIT-"FIRENZE CERTOSA"
      

      BY CAR

      • How to get to SIENA-FACULTY-OF-ENGINEERING A1-exit "FIRENZE-CERTOSA" by car

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  To get in touch with me email to: M y  L A S T  N A M E a t  acm.org OR unisi.it OR dii.unisi.it OR ieee.org OR computer.org