Università degli Studi di Siena
Facoltà di Ingegneria
Insegnamento di
Reconfigurable Computing
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  • L'inizio del corso e' previsto (regolarmente) per il 27/01/2010 (calendario lezioni in aggiornamento).
  • Gli studenti sono invitati a registarsi su questo sito per una migliore organizzazione del corso.
  • AULE: da stabilire.
The recent growth in both size and speed of FPGAs (Field Programmable Gate Arrays) have opened up tremendous opportunities for using these as spatial computing platforms in the form of hardware accelerators on applications ranging from image and video processing, cryptography, bioinformatics, high-performance computing, molecular dynamics, data bases, information retrieval etc. These implementations have routinely demonstrated speedups of two or more orders of magnitude. This course looks at FPGAs as code accelerators and what opportunities they offer, the challenges to be overcome and what role they can play in a post Moore's Law era. Relevant topics include architecture, languages and compilation, run-time systems, algorithms and data representation.
Brief look at FPGA structure and architectures and Hardware. Description Languages (HDLs). Review of applications using FPGA as code accelerators. Platforms for reconfigurable computing: SGI RASC, Intel QuickAssist. Programming FPGAs, HDLs or HLLs? New algorithmic approaches for spatial computing? Open research issues.