Roberto Giorgi's Papers

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INTELLECTUAL PROPERTY: Software Copyrights

IP2) [Bartolini06e]
S. Bartolini, P. Bennati, R. Giorgi, "BlueSign 2", SIAE 24-02-2006/001, Reg. 24 Feb. 2006.
BibTeX entry: Bartolini06e.bib.

IP1) [Bennati03a]
P. Bennati, T. Capasso, V. Di Massa, F. Giallombardo, R. Giorgi, M. Guerrini, E. Maggio , N. Nannetti, "BlueSign Translator", SIAE 002568, Ord. D003454, Reg. 21 Mar. 2003.
Abstract, PDF. BibTeX entry: Bennati03a.bib.

PAPERS: International and National Journals

J16) [Bartolini08a]
S. Bartolini, I. Branovic, R. Giorgi, E. Martinelli, "Effects of Instruction-set Extensions on an Embedded Processor: a Case Study on Elliptic Curve Cryptography over GF(2/sup m/)", IEEE Trans. Computers, ISSN:0018-9340, Los Alamitos, CA, USA, vol. 57, no. 5, May 2008, pp. 672-685, doi 10.1109/TC.2007.70832.
Abstract, PDF. BibTeX entry: Bartolini08a.bib.

J15) [Bartolini07a]
S. Bartolini, P. Bennati, R. Giorgi, "L'Informatica per i sordi: su palmare la lingua dei segni", Mondo Digitale, June 2007, pp. 42-49.
Abstract, PDF. BibTeX entry: Bartolini07a.bib.

J14) [Bartolini06d]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "MEmory performance: DEaling with Applications, systems and architecture", ACM SIGARCH Computer Architecture News, ISSN:0163-5964, New York, NY, USA2, vol. 34, no. 1, Mar. 2006, pp. 1-2, doi 10.1145/1152779.1147352.
Abstract, PDF. BibTeX entry: Bartolini06d.bib.

J13) [Bartolini06b]
S. Bartolini, R. Giorgi, "Issues in Embedded Single-Chip Multicore Architectures", Journal of Embedded Computing, ISSN:1740-4460, Amsterdam, Netherlands, vol. 2, no. 2, Dec. 2006, pp. 137-139.
Abstract, PDF. BibTeX entry: Bartolini06b.bib.

J12) [Foglia05a]
P. Foglia, R. Giorgi, C. A. Prete, "Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload", ELSEVIER Journal of Parallel and Distributed Computing, ISSN:0743-7315, Amsterdam, Netherlands, vol. 65, no. 3, Mar. 2005, pp. 289-306, doi 10.1016/j.jpdc.2004.10.003.
Abstract, PDF. BibTeX entry: Foglia05a.bib.

J11) [Foglia04b]
P. Foglia, R. Giorgi, C. A. Prete, "Speeding-up multiprocessors running DBMS workloads through coherence protocol", Int. J. High Performance Computing and Networking, , ISSN:1740-0562, Olney, Bucks. (UK), vol. 1, no. 1/2, June 2004, pp. 17-32, doi 10.1504/IJHPCN.2004.007562.
Abstract, PDF. BibTeX entry: Foglia04b.bib.

J10) [Branovic04b]
I. Branovic, R. Giorgi, E. Martinelli, "A Workload Characterization of Elliptic Curve Cryptography Methods in Embedded Environments", ACM SIGARCH Computer Architecture News, ISSN:0163-5964, New York, NY, USA, vol. 32, no. 3, June 2004, pp. 27-34, doi 10.1145/1024295.1024299.
Abstract, PDF. BibTeX entry: Branovic04b.bib.

J9) [Foglia04a]
P. Foglia, R. Giorgi, C. A. Prete, "Simulation Study of Memory Performance of SMP Multiprocessors Running a TPC-W Workload", IEE Proceedings Computers and Digital Techniques, ISSN:1350-2387, London, UK, vol. 151, no. 2, Mar. 2004, pp. 93-109, doi 10.1049/ip-cdt:20040349 .
Abstract, PDF. BibTeX entry: Foglia04a.bib.

J8) [Bartolini01a]
S. Bartolini, R. Giorgi, J. Protic, C. A. Prete , M. Valero, "Parallel Architecture and Compilation Techniques: Selection of workshop papers, Guests' Editors Introduction", ACM SIGARCH Computer Architecture News, ISSN:0163-5964, New York, NY, USA, vol. 29, no. 5, Dec. 2001, pp. 9-12, doi 10.1145/563647.563651.
Abstract, PDF. BibTeX entry: Bartolini01a.bib.

J7) [Kavi01a]
Krishna M. Kavi, Roberto Giorgi, Joseph Arul, "Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation", IEEE Trans. Computers, ISSN:0018-9340, Los Alamitos, CA, USA, vol. 50, no. 8, Aug. 2001, pp. 834-846, doi 10.1109/12.947003.
Abstract, PDF. BibTeX entry: Kavi01a.bib.

J6) [Giorgi01a]
R. Giorgi, "Memory Decoupled Architectures and related issues Guest Editor's Introduction", IEEE TCCA Newsletter, ISSN:1041-1186 , Los Alamitos, CA, USA, Jan. 2001, pp. 2-4.
Abstract, PDF. BibTeX entry: Giorgi01a.bib.

J5) [Kavi00a]
K. Kavi, J. Arul, R. Giorgi, "Execution and Cache Performance of the Scheduled Dataflow Architecture", SPRINGER Journal of Universal Computer Science, ISSN:0948-6968, New York, NY, (USA), vol. 6, no. 10, Oct. 2000, pp. 948-967, doi 10.3217/jucs-006-10-0948, Special Issue on Multithreaded Processors and Chip Multiprocessors.
Abstract, PDF. BibTeX entry: Kavi00a.bib.

J4) [Giorgi99a]
Roberto Giorgi, Cosimo Antonio Prete, "PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors", IEEE Trans. Parallel and Distributed Systems, Vol. 10, No. 7, ISSN:1045-9219, Los Alamitos, CA, USA, July 1999, pp. 742-763, doi 10.1109/71.780868.
Abstract, PDF. BibTeX entry: Giorgi99a.bib.

J3) [Giorgi99c]
R. Giorgi, C.A. Prete, "An Educational Environment for Designing and Performance Tuning of Embedded Systems", IEEE TCCA Newsletter, ISSN:1041-1186 , Los Alamitos, CA, USA, Feb. 1999, pp. 54-56, doi 10.1145/1275182.1275211.
Abstract, PDF. BibTeX entry: Giorgi99c.bib.

J2) [Giorgi97e]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi, "Trace Factory: Generating Workloads for Trace-Driven Simulation of Shared-Bus Multiprocessors", IEEE Concurrency, ISSN:1092-3063, Los Alamitos, CA, USA, vol. 5, no. 4, Oct. 1997, pp. 54-68, doi 10.1109/4434.641627.
Abstract, PDF. BibTeX entry: Giorgi97e.bib.

J1) [Prete97a]
C. A. Prete, G. Prina, R. Giorgi, L. Ricciardi, "Some Considerations About Passive Sharing in Shared-Memory Multiprocessors", IEEE TCCA Newsletter, ISSN:1041-1186, Los Alamitos, CA, USA, Mar. 1997, pp. 34-40.
Abstract, PDF. BibTeX entry: Prete97a.bib.

BOOKS and BOOK'S CHAPTERS

B5) [Bartolini09b]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "MEDEA '09: Proc. 2009 workshop on MEmory performance", ACM, ISBN:978-1-60558-830-8, New York, NY, USA, Sept. 2009, pp. 1-48, doi 10.1145/1621960.
BibTeX entry: Bartolini09b.bib.

B4) [Bartolini09a]
S. Bartolini, R. Giorgi, E. Martinelli, "Cryptographic Engineering", Springer, ISBN:978-0-387-71816-3, 2009, pp. 191-233, doi 10.1007/978-0-387-71817-0.
PDF. BibTeX entry: Bartolini09a.bib.

B3) [Bartolini08b]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "MEDEA '08: Proc. 2008 workshop on MEmory performance", ACM, ISBN:978-1-60558-243-6, New York, NY, USA, Oct. 2008, pp. 1-84, doi 10.1145/1509084.
BibTeX entry: Bartolini08b.bib.

B2) [Bartolini07b]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "MEDEA '07: Proc. 2007 workshop on MEmory performance", ACM, ISBN:978-1-9593-807-7, New York, NY, USA, 2007, pp. 1-113, doi 10.1145/1327171.
BibTeX entry: Bartolini07b.bib.

B1) [Bartolini06f]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "Proc. 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures", ACM Press, ISBN:1-59593-568-1, New York, NY, U.S.A., 2006, pp. 1-52, doi 10.1145/1166133.
BibTeX entry: Bartolini06f.bib.

PAPERS: International and National Conference Proceedings

C45) [Stavrou09a]
K. Stavrou, D. Pavlou, M. Nikolaides, P. Petrides , P. Evripidou, P. Trancoso, Z. Popovic, R. Giorgi, "Programming Abstractions and Toolchain for Dataflow Multithreading Architectures", IEEE Proc. Eighth Int.l Symp. on Parallel and Distributed Computing (ISPDC 2009), ISBN:978-0-7695-3680-4, Lisbon, Portugal, July 2009, pp. 107-114, doi 10.1109/ISPDC.2009.35.
Abstract, PDF. BibTeX entry: Stavrou09a.bib.

C44) [Giorgi09c]
R. Giorgi, Z. Popovic, N. Puzovic, "Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture", Proc. 9th Int.l Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2009, ISBN:978-3-642-03137-3, Samos, Greece2, July 2009, pp. 78-87, doi 10.1007/978-3-642-03138-0.
Abstract, PDF. BibTeX entry: Giorgi09c.bib.

C43) [Giorgi09b]
R. Giorgi, Z. Popovic, N. Puzovic, "Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture", Proc. IEEE Int.l Symp. on Parallel and Distributed Processing - MTAAP Multi-Threading Architectures and APplications, ISBN:978-1-4244-3751-1, ISSN:1530-2075, Rome, Italy, May 2009, pp. 1-8, doi 10.1109/IPDPS.2009.5161111 .
Abstract, PDF. BibTeX entry: Giorgi09b.bib.

C42) [Giorgi09a]
R. Giorgi, Z. Popovic, N. Puzovic, "Introducing hardware TLP support for the Cell processor", Proc. IEEE Int.l Workshop on Multi-Core Computing Systems, ISBN:978-1-4244-3569-2, Fukuoka, Japan, Mar. 2009, pp. 657-662, doi 10.1109/CISIS.2009.177.
Abstract, PDF. BibTeX entry: Giorgi09a.bib.

C41) [Giorgi08a]
R. Giorgi, P. Bennati, "Filtering drowsy instruction cache to achieve better efficiency", SAC '08: Proc. 2008 ACM symposium on Applied computing, ISBN:978-1-59593-753-7, New York, NY, USA, Mar. 2008, pp. 1554-1555, doi 10.1145/1363686.1364050.
Abstract, PDF. BibTeX entry: Giorgi08a.bib.

C40) [Giorgi08e]
R. Giorgi, P. Bennati, "Reducing Leakage through Filter Cache", Proc. 11th EUROMICRO-DSD, ISBN:978-1-59593-753-7, Parma, Italy, Sept. 2008, pp. 334-341, doi 10.1109/DSD.2008.123.
Abstract, PDF. BibTeX entry: Giorgi08e.bib.

C39) [Giorgi08d]
R. Giorgi, Z. Popovic, N. Puzovic, A. Azavedo and B. Juurlink, "Analyzing Scalability of Deblocking Filter of H.264 via TLP exploitation in a new many-core architecture", Proc. 11th EUROMICRO-DSD, ISBN:978-1-59593-753-7, Parma, Italy, Sept. 2008, pp. 189-194, doi 10.1109/DSD.2008.93.
Abstract, PDF. BibTeX entry: Giorgi08d.bib.

C38) [Giorgi08c]
R. Giorgi, Z. Popovic, N. Puzovic, "Implementing DTA support in CellSim", HiPEAC ACACES-2008, ISBN:978-90-382-1288-3, L'Aquila, Italy, July 2008, pp. 159-162.
Abstract, PDF. BibTeX entry: Giorgi08c.bib.

C37) [Giorgi08b]
R. Giorgi, Z. Popovic, N. Puzovic, A. Azavedo and B. Juurlink, "Exploiting Parallelism of Deblocking Filter of H.264 on DTA architecture", HiPEAC ACACES-2008, ISBN:978-90-382-1288-3, L'Aquila, Italy, July 2008, pp. 55-58.
Abstract, PDF. BibTeX entry: Giorgi08b.bib.

C36) [Giorgi07a]
R. Giorgi, Z. Popovic, N. Puzovic, "DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems", Proc. IEEE SBAC-PAD, ISBN:0-7695-23014-1, Gramado, Brasil, Oct. 2007, pp. 263-270, doi 10.1109/SBAC-PAD.2007.27.
Abstract, PDF. BibTeX entry: Giorgi07a.bib.

C35) [Giorgi07b]
R. Giorgi, P. Bennati, "Reducing leakage in power-saving capable caches for embedded systems by using a filter cache", Proc. ACM MEDEA, ISBN:978-1-59593-807-7, Brasov, Romania, Sept. 2007, pp. 105-112.
Abstract, PDF. BibTeX entry: Giorgi07b.bib.

C34) [Giorgi07c]
R. Giorgi, Z. Popovic, N. Puzovic, "Decoupled Threaded Architecture", HiPEAC ACACES-2007, ISBN:97-890-382-1127-5, L'Aquila, Italy, July 2007, pp. 119-121.
Abstract, PDF. BibTeX entry: Giorgi07c.bib.

C33) [Bennati07a]
P. Bennati, R. Giorgi, "Adaptive Cache Decay", HiPEAC ACACES-2007, ISBN:97-890-382-1127-5, L'Aquila, Italy, July 2007, pp. 1-4.
Abstract, PDF. BibTeX entry: Bennati07a.bib.

C32) [Giorgi06b]
R. Giorgi, N. Puzovic, "Scheduling and NoC Traffic Reduction in T-SDF Architecture", HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila, Italy, July 2006, pp. 253-256.
Abstract, PDF. BibTeX entry: Giorgi06b.bib.

C31) [Giorgi06a]
R. Giorgi, Z. Popovic, "Core Design and Scalability of Tiled SDF Architecture", HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila, Italy2, July 2006, pp. 145-148.
Abstract, PDF. BibTeX entry: Giorgi06a.bib.

C30) [Bennati06a]
P. Bennati, R. Giorgi, "JCacheSim: simulatore visuale di gerarchia di memoria con interprete per programmi MIPS", AICA Didamatica, Cagliari, Italy, May 2006, pp. 105-114.
Abstract, PDF. BibTeX entry: Bennati06a.bib.

C29) [Bartolini06c]
S. Bartolini, P. Bennati, R. Giorgi, "BLUESIGN: traduttore multimediale portatile per non udenti", AICA Didamatica, Cagliari, Italy, May 2006, pp. 17-24.
Abstract, PDF. BibTeX entry: Bartolini06c.bib.

C28) [Bartolini06a]
S. Bartolini, P. Bennati, R. Giorgi, E. Martinelli, "Elliptic Curve Cryptography support for ARM based Embedded systems", HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila, Italy, July 2006, pp. 13-16.
Abstract, PDF. BibTeX entry: Bartolini06a.bib.

C27) [Bartolini05c]
S. Bartolini, P. Bennati, R. Giorgi, "Bluesign-2, il nuovo visualizzatore portatile per la Lingua Italiana dei Segni", Atti del 51esimo Convegno Nazionale di Studio ed Aggiornamento AIES, S. Pellegrino (BG), Italy, Aug. 2005, pp. 140-145.
Abstract, PDF. BibTeX entry: Bartolini05c.bib.

C26) [Bartolini05b]
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic, "Recent Proposals for Tiled Architectures", HiPEAC ACACES-2005, ISBN:90-382-0802-2, L'Aquila, Italy, July 2005, pp. 47-50.
Abstract, PDF. BibTeX entry: Bartolini05b.bib.

C25) [Alioto05a]
M. Alioto, S. Bartolini, P. Bennati, R. Giorgi, "New techniques for low power caches", HiPEAC ACACES-2005, ISBN:90-382-0802-2, L'Aquila, Italy, July 2005, pp. 133-136.
Abstract, PDF. BibTeX entry: Alioto05a.bib.

C24) [Bartolini04a]
S. Bartolini, I. Branovic, R. Giorgi, E. Martinelli, "A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields", IEEE 16th Symp. on Computer Architecture and High Performance Computing (SBAC-PAD-04), ISBN:0-7695-2240-8, ISSN:1550-6533, Foz do Iguacu, Brasil, Oct. 2004, pp. 238-245, doi 10.1109/SBAC-PAD.2004.5.
Abstract, PDF. BibTeX entry: Bartolini04a.bib.

C23) [Bartolini04b]
S. Bartolini, P. Bennati, R. Giorgi, "Sistema per la traduzione in Lingua Italiana dei Segni: Blue Sign Translator / Wireless Sign System", Atti del 50esimo Convegno Nazionale di Studio ed Aggiornamento AIES, Chianciano Terme - Siena, Italy, Aug. 2004, pp. 203-212.
Abstract, PDF. BibTeX entry: Bartolini04b.bib.

C22) [Branovic04a]
I. Branovic, R. Giorgi, E. Martinelli, "WebMIPS: A New Web-Based MIPS Simulation Environment for Computer Architecture Education.", IEEE Workshop on Computer Architecture Education (WCAE-04), Munich, Germany, June 2004, pp. 93-98.
Abstract, PDF. BibTeX entry: Branovic04a.bib.

C21) [Foglia03a]
P. Foglia, R. Giorgi, C.A. Prete, "Speeding-up Multiprocessors Running DSS Workloads through Coherence Protocols", 2nd Workshop on Hardware Software Support for Parallel and Distributed Scientific and Engineering Computing (SHPSEC-03), New Orleans, LA, USA, Sept. 2003, pp. 124-149.
Abstract, PDF. BibTeX entry: Foglia03a.bib.

C20) [Branovic03a]
I. Branovic, R. Giorgi, E. Martinelli, "Memory Performance of Public-Key cryptography Methods in Mobile Environments", ACM SIGARCH Workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA-03), New Orleans, LA, USA, Sept. 2003, pp. 24-31.
Abstract, PDF. BibTeX entry: Branovic03a.bib.

C19) [Foglia02a]
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, "Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture", Springer-Verlag LNCS Workshop on Web Engineering (WWE-02), ISBN:3-540-44177-8, Pisa, Italy, vol. 2376, May 2002, pp. 134-146.
Abstract, PDF. BibTeX entry: Foglia02a.bib.

C18) [Branovic02a]
I. Branovic, R. Giorgi, C.A. Prete, "Web-based training on Computer Architecture: The case for JCachesim", IEEE Workshop on Computer Architecture Education (WCAE-02), Anchorage, AK, USA, May 2002, pp. 56-60.
Abstract, PDF. BibTeX entry: Branovic02a.bib.

C17) [Kavi01b]
K. Kavi, J. Arul, R. Giorgi, "Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications", 14th Int.l Conf. on Parallel and Distributed Computing Systems (ISCA-PDCS-01), ISBN:1-880843-39-0, Richardson, TX, USA, Aug. 2001, pp. 365-371.
Abstract, PDF. BibTeX entry: Kavi01b.bib.

C16) [Foglia01e]
P. Foglia, R. Giorgi, C.A. Prete, "OS Effects on Memory Hierarchy of a SMP Multiprocessor Running a DBMS Workload", Int.l Conf. on Advances in Infrastructure for E-Business, Science, and Education (SSGRR-01), ISBN:88-85280-61-7, L'Aquila, Italy, Aug. 2001, pp. 1-8 (cdrom).
Abstract, PDF. BibTeX entry: Foglia01e.bib.

C15) [Foglia01d]
P. Foglia, R. Giorgi, C. Prete, "Accelerating DSS Workloads through Coherence Protocols", ACM Workshop on Caching and Coherence Consistency (WC3-01), Sorrento, Italy, June 2001, pp. G.1-G.8.
Abstract, PDF. BibTeX entry: Foglia01d.bib.

C14) [Foglia01c]
P. Foglia, R. Giorgi, C.A. Prete, "Performance Analysis of Parallel Applications Running on SMP", Int.l Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA-01), ISBN:1-892512-70-X, Las Vegas, NV, USA, vol. IV, June 2001, pp. 1634-1640.
Abstract, PDF. BibTeX entry: Foglia01c.bib.

C13) [Foglia01a]
P. Foglia, R. Giorgi, C. Prete, "Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload", IEEE Proc. 34th Annual Hawaii Int.l Conf. on System Sciences (HICSS-34), ISBN:0-7695-0981-9, Maui, Hawaii, USA, vol. 7, Jan. 2001, pp. 2544-2552.
Abstract, PDF. BibTeX entry: Foglia01a.bib.

C12) [Kavi00b]
K. Kavi, R. Giorgi, J. Arul, "Comparing Execution Performance of Scheduled Dataflow Architecture with RISC Processors", Proc. 13th ISCA Parallel and Distributed Computing Systems Conf. (ISCA-PDCS-00), ISBN:1-880843-34-X, Las Vegas, NV, USA, Aug. 2000, pp. 41-47.
Abstract, PDF. BibTeX entry: Kavi00b.bib.

C11) [Foglia00a]
P. Foglia, R. Giorgi, C.A. Prete, "Performance Analysis of Electronic Commerce Multiprocessor Servers", IEEE Proc. 33th Annual Hawaii Int.l Conf. on System Sciences (HICSS-33), ISBN:0-7695-0493-0, Maui, Hawaii, USA, Jan. 2000, pp. 2214-2222.
Abstract, PDF. BibTeX entry: Foglia00a.bib.

C10) [Foglia99a]
P. Foglia, R. Giorgi, C.A. Prete, "Process Migration Effects on Memory Performance of Multiprocessor Web-Server", Springer-Verlag LNCS Proc. High Performance Computing Conf. (HIPC-99), ISBN:3-540-66907-8, Calcutta, India, vol. 1745, Dec. 1999, pp. 133-142.
Abstract, PDF. BibTeX entry: Foglia99a.bib.

C9) [Giorgi99d]
R. Giorgi, C.A. Prete, "A Coherence Protocol for the Elimination of Passive Sharing in Single and Multiple Threaded Shared-Bus Shared-Memory Multiprocessors", Eighth Workshop on Scalable Shared Memory Multiprocessors (WSSMM-99), Atlanta, Georgia, May 1999, pp. 29.
Abstract, PDF. BibTeX entry: Giorgi99d.bib.

C8) [Giorgi98b]
R. Giorgi, C.A. Prete, "An Educational Environment for Designing and Performance Tuning of Embedded Systems", IEEE Workshop on Computer Architecture Education (WCAE-98), Barcelona, Spain, June 1998, pp. VII/A.1-6.
Abstract, PDF. BibTeX entry: Giorgi98b.bib.

C7) [Foglia98a]
P. Foglia, R. Giorgi, C.A. Prete, "Analysis of Sharing Overhead in Shared Memory Multiprocessors", IEEE Proc. 31st Annual Hawaii Int.l Conf. on System Sciences (HICSS-31), ISBN:0-8186-8255-8, Big Island, Hawaii, USA, vol. 7, Jan. 1998, pp. 776-777.
Abstract, PDF. BibTeX entry: Foglia98a.bib.

C6) [Giorgi97f]
R. Giorgi, C.A. Prete, G. Prina, "An Educational Environment for Program Behavior Analysis and Cache Memory Design", IEEE Proceedings Int.l Conf. on Frontiers in Education (FIE-97), ISBN:0-7803-4086, Pittsburgh, PA, USA, Nov. 1997, pp. 1243-1248.
Abstract, PDF. BibTeX entry: Giorgi97f.bib.

C5) [Giorgi97c]
R. Giorgi, P. Foglia, C.A. Prete, "Bus Utilization Analysis of Multithreaded Shared-Bus Multiprocessors: Initial Results", IASTED Proc. 9th Int.l Conf. on Parallel and Distributed Computing and Systems (IPDCS-97), ISBN:0-88986-240-0, Washington, DC, USA, Oct. 1997, pp. 24-29.
Abstract, PDF. BibTeX entry: Giorgi97c.bib.

C4) [Giorgi97b]
R. Giorgi, C.A. Prete, G. Prina, "Cache Memory Design for Embedded Systems Based on Program Locality Analysis", IEEE Proc. Int.l Conf. on Microelectronic System Education (MSE-97), ISBN:0-8186-7996-4, Arlington, VA, USA, July 1997, pp. 16-18.
Abstract, PDF. BibTeX entry: Giorgi97b.bib.

C3) [Giorgi97d]
R. Giorgi, C.A. Prete, G. Prina, "An approach for investigating design and tuning performance of embedded systems", EAEEIE Proc. Int.l Conf. on Innovation and Quality in Education for Electrical and Information Engineering, Edinburgh, Scotland, UK, June 1997, pp. G1.15-20.
Abstract, PDF. BibTeX entry: Giorgi97d.bib.

C2) [Giorgi97a]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi, "A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessor", IEEE Proc. 30th Hawaii Int.l Conf. on System Sciences (HICSS-30), ISBN:0-8186-7734-1, Maui, Hawaii, vol. 1, Jan. 1997, pp. 266-275, Best mini-track paper award.
Abstract, PDF. BibTeX entry: Giorgi97a.bib.

C1) [Giorgi96a]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi, "A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors", IEEE Proc. 22nd EuroMicro Int.l Conf. (EM-96), ISBN:0-8186-7487-3, Prague, Ceck Republic, Sept. 1996, pp. 207-214, doi 10.1109/EURMIC.1996.546384.
Abstract, PDF. BibTeX entry: Giorgi96a.bib.

PAPERS: Miscellanous

M4) [Giorgi07d]
R. Giorgi, Z. Popovic, N. Puzovic, "Memory access decoupling in a multithreaded architecture", WIRTES 2007 - Primo Workshop Italiano su Real-Time Embedded Systems, Pisa, Italy, July 2007, pp. 1-11.
Abstract. BibTeX entry: Giorgi07d.bib.

M3) [Bartolini05a]
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic, "Tiled Architectures and Recent Proposals for Chip", , no. 5, May 2005, pp. 23.
Abstract, PDF. BibTeX entry: Bartolini05a.bib.

M2) [Giorgi99b]
Roberto Giorgi, "Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-BusMultithreaded Multiprocessors", University of Pisa, Dept. Ingegneria della Informazione, Ph.D. Thesis, Pisa, Italy, Jan. 1999, pp. 84.
Abstract, PDF. BibTeX entry: Giorgi99b.bib.

M1) [Giorgi95a]
Roberto Giorgi, "Valutazione delle Prestazioni di Sistemi Multiprocessore Basata sull'Analisi di Tracce Reali", University of Pisa, Dept. Ingegneria della Informazione, MS Thesis, Pisa, Italy, July 1995, pp. 96.
Abstract, PDF. BibTeX entry: Giorgi95a.bib.