Prof. Massimo Alioto

 

Associate Professor

Information Engineering Dept.

University of Siena
Via Roma, 56

53100 Siena (Italy)
 

Visiting professor

EECS - University of Michigan, Ann Arbor (USA)

1301 Beal Ave, Ann Arbor, MI 48109-2122

 

 

 

Contacts

VoIP:

   phone: +39 0577 234850 (ext. 1004)
   fax:     +39 0577 233602

 

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SHORT BIO:

Massimo Alioto was born in Brescia in 1972. He took the M.Sc. degree in Electronic Engineering in 1997, and the Ph.D. degree in 2001 from the University of Catania. In 2002, he joined the Department of Information Engineering of the University of Siena as a Research Associate, and in the same year as an Assistant Professor. In 2005 he is appointed Associate Professor in Italy, and is engaged in 2006 by the Faculty of Engineering of the University of Siena. In the summer of 2007, he was visiting professor at EPFL - Lausanne (Switzerland). In 2009-2011, he was visiting professor at the Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley. Since 2011, he is visiting professor at the University of Michigan, Ann Arbor.

 

His research interests involve VLSI design from transistor to micro-architectural level, power harvesting/conversion/management in sub-mW systems and techniques for aggressive voltage scaling. In particular, his research activity is focused on:

·        Design of ultra low-power circuits and systems for distributed sensing and ubiquitous computing

·        Ultra-low power modules for self-powered wireless nodes (power management, power delivery, fully-digital ADCs, security, energy scavenging)

·        VLSI design for ultra-high energy efficiency and resiliency in near-threshold circuits for green computing

·        Error-aware and widely energy-scalable VLSI circuits for wide/adaptive management of the error rate-energy-performance tradeoff

·        Leakage- and variability-aware design methodologies for high-performance digital circuits

·        Analysis and design of digital circuits in emerging technologies (FinFET, Ge MOSFET, Si-Ge MOSFET, Tunnel FETs)

 

He is author or co-author of about 170 papers on international journals (60, mostly IEEE Transactions) and international conferences. Two of them are among the 25 most downloaded IEEE TVLSI papers in 2007 (respectively the 10th and 13th). He is also coauthor of the book  "MODEL AND DESIGN OF BIPOLAR AND MOS CURRENT-MODE LOGIC: CML, ECL and SCL Digital Circuits" (Springer). He is an IEEE Senior Member.

 

Since 2001 he has been teaching several courses on Basic Electronics, Microelectronics, Digital VLSI Electronics at University of Catania and Siena, other than the post-graduate master "Sicurnet". He has also given several invited seminars in several universities and conference throughout Europe and US. He is the director of the Electronics and Measurements Lab in the Engineering faculty of Siena (site of Arezzo).

 

He is Distinguished Lecturer by the IEEE Circuits and Systems Society for years 2009 and 2010. He regularly gives tutorials and keynote speeches at international conferences (ISCAS, ICECS, ICM, LASCAS), and seminars at universities and companies (IBM, Intel, Qualcomm).  In 2010, he received the ISCAS 2010 Best Tutorial award for the tutorial “Pushing the Limits of Energy Consumption: Opportunities and Challenges in Subthreshold Logic” (an overview paper to TCAS-I was also invited, to be printed on Jan. 2012).

He was also Program Co-Chair for the IEEE Summer School on “Pushing the boundaries of energy efficiency in low power design”, held in Cuzco (Peru) in Jan. 17-21, 2011.

 

He is Associate Editor of the following international journals:

-  IEEE Transactions on VLSI Systems (2009-present)

- ACM Transactions on Design Automation of Electronic Systems (2011-present)

- IEEE Transactions on Circuits and Systems – part I (2012-present)

- Microelectronics Journal (2008-present)

- Integration, the VLSI Journal (2008-present)

- Journal of Circuits, Systems, and Computers (2007-present)

- Journal of Low Power Electronics and Applications (2010 - present)

- Journal of Low Power Electronics (2011-present)

 

He is also Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CAS Society, as well as:

§   Member of the IEEE CASS DLP coordinating committee (2011-present)

§  Technical Program Chair for

o   ICM 2010 (Cairo, Egypt)

o   NEWCAS 2012 (Montreal, Canada)

 

§  Track Chair for the following international conferences:

o   ICECS 2012 for the area “VLSI Systems, Architecture and Applications”

o   ICCD 2012 for the area “Logic and Circuits”

o   ISCAS 2012 for the area “VLSI Systems and Applications”

o   MWSCAS 2012

o   APCCAS 2012

o   ISCAS 2011 for the area “VLSI Systems and Applications”

o   ICCD 2011 for the area “Logic and Circuits”

o   ISCAS 2010 for the area “VLSI Systems and Applications”

o   ICCD 2010 for the area “Logic and Circuits”

o   ICM 2009 for the area “Circuit design”

o   ISCAS 2009 for the area “VLSI Systems and Applications” (2008)

o   ICECS 2007 for the area “Digital circuits” (2007)

 

§  Tutorials Chair for the ICECS 2011 conference

§  Special Session Chair for the ISCAS 2012 conference

§  Member of the Musyc FCRP Center (US)

§  Guest Editor of the special issue on “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers (2010)

§  TPC member for the following international conferences:

o   ECCTD 2011, ASQED2010, Computer Design & VLSI Symposium (a part of the World Congress on Computer Science and Information Engineering – CSIE) (2009), ICM (2008 - present), ICCD (2008 - present), PATMOS (2005 - 2006)

§  Chairman of the following special invited sessions:

o   “Emerging technologies for nanometer VLSI circuits and applications” (ISCAS 2010)

o   “Sub-Threshold Design for Ultra Low Power and Ultra-Dynamic Voltage Scaling” (ISCAS 2009)

 

§  Member of the Steering Committee for the LASCAS 2013 conference

 

 

RECENT JOURNAL/CONFERENCE PUBLICATIONS (SINCE YEAR 2006) - to get the full list, click here

International journals

F. Crupi, Member, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, G. Groeseneken, “Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements,” in print on IEEE Trans. on Circuits and Systems – part II

M. Alioto, G. Palumbo, M. Pennisi, “A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates,” in print on IEEE Trans. on Circuits and Systems – part I

F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling,” in print on IEEE Trans. on VLSI Systems

D. Baccarin, D. Esseni, M. Alioto, “Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks,” in print on IEEE Trans. on VLSI Systems

F. Frustaci, M. Alioto, P. Corsonello, “Tapered-Vth Approach for Energy-Efficient CMOS Buffers,” in print on IEEE Trans. on Circuits and Systems – part I

M. Alioto, E. Consoli, G. Palumbo, “From Energy-Delay Metrics to Constraints on the Design of Digital Circuits,” in print on International Journal of Circuit Theory and Applications.

M. Alioto, “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” in print on IEEE Trans. on Circuits and Systems – part I (invited extended paper).

M. Alioto, ”Modeling Strategies of the Input Admittance of RC Interconnects for VLSI CAD Tools,” Microelectronics Journal (Elsevier), vol. 42, no. 1, pp. 63-73, Jan. 2011.

M. Alioto, M. Poli, G. Palumbo, ”Optimized Design of Parallel Carry-Select Adders,” in print on Integration – the VLSI Journal (Elsevier).

M. Alioto, S. Badel, Y. Leblebici, ”Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff,” in print on Microelectronics Journal (Elsevier).

P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, ” Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements,” in print on IEEE Trans. on VLSI Systems

M. Alioto, ”Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells,” in print on IEEE Trans. on VLSI Systems

M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II – Results and Figures of Merit,” in print on IEEE Trans. on VLSI Systems

M. Alioto, E. Consoli, G. Palumbo, ”Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies,” in print on IEEE Trans. on VLSI Systems

M. Alioto, “Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1597-1607, July 2010.

M. Alioto, E. Consoli, G. Palumbo, “General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1583-1596, July 2010.

M. Alioto, E. Consoli, G. Palumbo, “Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 6, pp. 1273-1286, June 2010.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy,” in the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 879-895, 2010.

M. Alioto, G. Palumbo, M. Poli, “Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates,” in print on International Journal of Circuit Theory and Applications

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic Circuits,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 2, pp. 355-367, Feb. 2010.

M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 697-710, May 2010.

M. Alioto, M. Poli, S. Rocchi, “A general power model of Differential Power Analysis attacks to static logic circuits,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 711-724, May 2010.

A. Tajalli, M. Alioto, Y. Leblebici, “Improving power-delay performance of ultralow-power subthreshold SCL circuits,” IEEE Trans. on Circuits and Systems – part II, vol. 56, no. 2, pp. 127-131, Feb. 2009.

M. Alioto, M. Poli, S. Rocchi, “Differential Power Analysis Attacks to Precharged Busses: a General Analysis for Symmetric-Key Cryptographic Algorithms,” IEEE Trans. on Dependable and Secure Computing, vol. 7, no. 3, pp. 226-239, July-Sept. 2010.

M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology," IEEE Trans. on VLSI Systems, vol.18, no.2, pp. 232-245, Feb. 2010.

M. Alioto, G. Palumbo, M. Poli, "Analysis and Modeling of Energy Consumption in RLC Tree Circuits," IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291, Feb. 2009.

M. Alioto, G. Palumbo, "Power-Aware Design of Nanometer MCML Tapered Buffers," IEEE Trans. on Circuits and Systems – part II, vol. 55, no. 1, pp. 16-20, Jan. 2008.

M. Alioto, G. Palumbo, "Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders," IEE Electronics letters, vol. 43, no. 13, pp. 707-709, 21st June 2007.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Power-Delay-Area-Noise Margin Trade-offs in Positive-Feedback Source-Coupled Logic Gates," IEEE Trans. on Circuits and Systems – part I, vol. 54, no. 9,  pp. 1916-1928, Sept. 2007.

M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers," IEEE Trans. on Circuits and Systems – part II, vol. 54, no. 6, pp. 484-488, June 2007.

T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli, "A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map", IEEE Trans. on Circuits and Systems - part I, vol. 54, no. 4, pp. 816-828, April 2007.

M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits," Microelectronics Journal, vol. 38, no. 1, pp. 130-139, Jan. 2007.

M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison," IEEE Trans. on VLSI Systems, vol. 14, no. 12, pp. 1322-1335, Dec. 2006.

M. Alioto, G. Palumbo, "Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59, 2006.

M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1165-1169, Nov. 2006.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting Hysteresys in MCML Circuits", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1170-1174, Nov. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006.

M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC Tree Circuits", IEEE Trans. on VLSI Systems, vol. 14, no. 5, pp. 452-461, May 2006.

M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", IEE  Electronics Letters, vol. 42, no. 4, pp. 211- 212, 16th February 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE Transactions on CAS – Part II, vol. 53, no. 5, pp. 329-333, May 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator," IEEE Transactions on CAS – Part I, vol. 53, no. 2, pp. 326-337, Feb. 2006.

M. Alioto, G. Palumbo, "Modeling and Design Considerations on CML Gates under High-Current Effects," International Journal of Circuit Theory and Applications, vol. 33, no. 6, pp. 503-518, Nov./Dec. 2005.

M. Alioto, G. Palumbo, "Design strategies of Cascaded CML Gates," IEEE Transactions on CAS – part II, vol. 53,  no. 2,  pp. 85-89, Feb. 2006.

International conference proceedings

J. Richmond, M. John, L. Alarcon, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. R. Sanders, J. M. Rabaey, “Active RFID: A Perpetual Wireless Communications Platform for Sensors,” in print on Proc. of ESSCIRC 2012, Bordeaux (France), Sept. 2012.

M. Alioto, G. Palumbo, M. Pennisi, “A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic,” in Proc. of ISCAS 2012, pp. 1576-1579, Seoul (Korea), May 2012.

F. Crupi, P. Magnone, M. Alioto, J. Franco, G. Groeseneken, “Early Assessment of Emerging Technologies for VLSI Logic Circuits from Experimental Measurements,” in Proc. of ICSICT 2012 (invited).

E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional Push-Pull Pulsed Latch with 726 fJ•ps Energy Delay Product in 65nm CMOS,” in Proc. of ISSCC 2012, San Francisco (USA), Feb. 2012.

M. Alioto, “'Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells,” in Proc. of ECCTD 2011, pp. 557-561, Linkoping (Sweden), Aug. 2011.

F. Frustaci, P. Corsonello, M. Alioto, “Optimization and Evaluation of Tapered-VTH Approach for Energy-Efficient CMOS Buffers,” in print on Proc. of ECCTD 2011, Aug. 2011.

F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Experimental Analysis of Buried SiGe pMOSFETs from the Perspective of Aggressive Voltage Scaling,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011.

D. Baccarin, D. Esseni, M. Alioto, “A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011.

M. Alioto, E. Consoli, G. Palumbo, “DET FF Topologies: A Detailed Investigation in the Energy-Delay-Area Domain,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011.

F. Frustaci, P. Corsonello, M. Alioto, “Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011.

M. Djukanovic, L. Giancane, G. Scotti, A. Trifiletti, M. Alioto, “Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011.

M. Alioto, “Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010.

M. Alioto, E. Consoli, G. Palumbo, “Nanometer Flip-Flops Design in the E-D Space,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010.

M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010.

J. Mitard, L. Witters, M. Garcia Bardon, P. Christie, J. Franco, A. Mercha, P. Magnone, M. Alioto, F. Crupi, L.-A. Ragnarsson, A. Hikavyy, B. Vincent, T. Chiarella, R. Loo, J. Tseng, S. Yamaguchi, S. Takeoka, W.-W. Wang, P. Absil, T. Hoffmann, “Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD,” accepted to IEEE IEDM 2010, San Francisco (USA), Dec. 2010.

K. Agawa, M. Alioto, W. Zhou, T.-T. Liu, L. Alarcon, K. Hajkazemshirazi, M. John, J. Richmond, W. Li, J. Rabaey, “Design and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains,” in Proc. of SASIMI2010, Taipei (Taiwan), Oct. 2010.

M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits,” in print on Proc. of PATMOS 2010, Grenoble (France), Sept. 2010.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A Scalable Low-Entropy Detector to Counteract the Parameter Variability effects in TRBGs,” in print on Proc. IMTC 2010, Austin (USA), May 2010.

M. Merrett, Y. Wang, M. Alioto, M. Zwolinski, “Design Metrics for RTL Level Estimation of Delay Variability Due to Intradie (Random) Variations,” in Proc. of ISCAS 2010, pp. 2498-2501, Paris (France), May 2010.

P. Magnone, F. Crupi, M. Alioto, B. Kaczer, “Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits,” in Proc. of ISCAS 2010, pp. 1699-1702, Paris (France), May 2010.

M. Alioto, “Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology,” in Proc. of ISCAS 2010, pp. 3204-3207, Paris (France), May 2010.

M. Alioto, P. Bennati, R. Giorgi, “Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed,” in Proc. of ISCAS 2010, pp. 37-40, Paris (France), May 2010.

M. Alioto, “Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits,” in Proc. of ISCAS 2010, pp. 1468-1471, Paris (France), May 2010.

M. Alioto, E. Consoli, G. Palumbo, “Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency,” in Proc. of ISCAS 2010, pp. 321-324, Paris (France), May 2010.

M. Alioto, E. Consoli, G. Palumbo, “Optimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study,” in Proc. of ICECS 2009, pp. 275-278, Hammamet (Tunisia), Dec. 2009.

M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the Impact of Random Process Variations in CMOS Tapered Buffers,” in Proc. of ICECS 2009, pp. 57-60, Hammamet (Tunisia), Dec. 2009.

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Theoretical Analysis and Impact of Variations,” in Proc. of ICECS 2009, pp. 85-88, Hammamet (Tunisia), Dec. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Dependence of Differential Flip-Flops Performance on Clock Slope and Relaxation of Clock Network Design,” in Proc. of ICM 2009, pp. 110-113, Marrakech (Morocco), Dec. 2009.

M. Alioto, M. Poli, S. Rocchi, “Low-Overhead Countermeasures to protect Pre-charged Busses against Power Analysis Attacks,” in Proc. of ICM 2009, pp. 159-162, Marrakech (Morocco), Dec. 2009.

M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results,” in Proc. of ICM 2009, pp. 46-49, Marrakech (Morocco), Dec. 2009.

M. Alioto, “Analysis and Evaluation of Layout Density of FinFET Logic Gates,” in Proc. of ICM 2009, pp. 106-109,  Marrakech (Morocco), Dec. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,” in Proc. of ECCTD 2009, pp. 61-64, Antalya (Turkey), Aug. 2009.

M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, “Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits,” in Proc. of ECCTD 2009, pp. 779-782, Antalya (Turkey), Aug. 2009.

M. Alioto, E. Consoli, G. Palumbo, “Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits,” in Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009.

M. Alioto, Y. Leblebici, “Analysis and Design of Ultra-Low Power Subthreshold MCML Gates,” in Proc. of ISCAS 2009, pp. 2557-2560, Taipei (Taiwan), May 2009.

M. Alioto, “Understanding Loading Effects of RC Uniform Interconnects,” in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan), May 2009.

M. Alioto, S. Badel, Y. Leblebici, “Optimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff,” in Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009.

M. Alioto, “CAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies,” in Proc. of ICM 2008, pp. 154-157, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, M. Poli, G. Palumbo, “Compact and Simple Output Transition Time Model in Nanometer CMOS Gates,” in Proc. of ICM 2008, pp. 235-238, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, M. Poli, S. Rocchi, “Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA,” in Proc. of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008.

M. Alioto, Y. Leblebici, “Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits,” in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008. (INVITED)

Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici, “Design of High Performance Subthreshold Source-Coupled Logic Circuits,” in Proc. of PATMOS 2008, pp. 21-30, Lisbon (Portugal), Sep. 2008.

Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi, “Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction,” in Proc. of PATMOS 2008, pp. 31-41, Lisbon (Portugal), Sep. 2008.

M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic,” in Proc. of PATMOS 2008, pp. 136-145, Lisbon (Portugal), Sep. 2008.

M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the impact of process variations on static logic circuits versus fan-in,” in Proc. of ICECS 2008, pp. 137-140, Malta, Aug. 2008.

M. Alioto, G. Palumbo, M. Poli, “Energy Evaluation in RLC Tree Circuits with Exponential Input,” in Proc. of ICECS 2008, pp. 578-581, Malta, Aug. 2008.

M. Alioto, L. Fondelli, S. Rocchi, "Analysis and Performance Evaluation of Area-Efficient True Random Bit Generators on FPGAs", in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008.

A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J. Brauer, "Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage", in Proc. of ISCAS 2008, pp. 145-148, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, M. Poli, "Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs", in Proc. of ISCAS 2008, pp. 2865-2868, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, "Power-Delay Optimization in MCML Tapered Buffers", in Proc. of ISCAS 2008, pp. 141-144, Seattle (USA), May 2008.

M. Alioto, M. Poli, S. Rocchi, "A General Model for Differential Power Analysis Attacks to Static Logic Circuits", in Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008.

M. Alioto, G. Palumbo, M. Poli, "Efficient and Accurate Models of Output Transition Time in CMOS Logic", Proc. of ICECS 2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007.

M. Alioto, "A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic", Proc. of ICECS 2007, pp. 431-434, Marrakech (Morocco), Dec. 2007.

M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RLC Tree Circuits", Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain), Aug. 2007.

M. Alioto, G. Palumbo, "Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders", Proc. of ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms", Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug. 2007.

M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs", Proc. of ESSDERC 2007, pp. 191-194, Munich (Germany), Sept. 2007.

M. Alioto, G. Palumbo, "Delay Variability Due to Supply Variations in Transmission-Gate Full Adders", Proc. of ISCAS 2007, pp. 3732-3735, New Orleans (USA), May 2007.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Maximum-Period PRBGs Derived From A Piecewise Linear One-Dimensional Map", Proc. of ISCAS 2007, pp. 693-696, New Orleans (USA), May 2007.

M. Alioto, G. Palumbo, "High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology", Proc. of ISCAS 2007, pp. 2998-3001, New Orleans (USA), May 2007.

M. Alioto, G. Palumbo, "Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects", Proc. of SCAS 2007, pp. 3255-3258, New Orleans (USA), May 2007.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Mixed Techniques to Protect Precharged Busses against Differential Power Analisys Attacks", Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May 2007.

T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, "Implementation-Efficient Maximum-Period Nonlinear Congruential Generators", Proc. of IMTC 2007, Warsaw (Poland), May. 2007.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Efficient Post-Processing Module for a Chaos-based Random Bit Generator", Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec. 2006.

M. Alioto, G. Palumbo, "Modeling of Delay Variability due to Supply Variations in Pass-Transistor and Static Full Adders", Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006.

M. Alioto, R. Mita, G. Palumbo, "A Design Methodology for High-Speed Low-Power MCML Frequency Dividers", Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Entropy Enhancement in a Chaos-Based True Random Bit Generators", Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis", Proc. of PATMOS 2006, pp. 624-633, Montpellier (France), Sept. 2006.

M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm", Proc. of PATMOS 2006, pp. 593-602, Montpellier (France), Sept. 2006.

M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Technique to Design High Entropy Chaos-Based True Random Bit Generators", Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May 2006.

M. Alioto, G. Palumbo, M. Poli, "Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs", Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006.

M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Analysis and Design of MCML Gates with Hysteresis", Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006.

M. Alioto, G. Palumbo, "Nanometer MCML Gates: Models and Design Considerations", Proc. of ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006.

M. Alioto, G. Palumbo, "Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders", Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006.

T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Uniform-Distributed Noise Generator Based on a Chaotic Circuit", Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006.

 

 

 

 

 

 

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My bookmarks:

IEEE Trans. on VLSI Systems                     Microelectronics Journal                    Integration – the VLSI Journal

IEEE Trans. on CAS – part I                       IEEE Trans. on CAS – part II           Int. Journal of Circuit Theory and Applications

VSA-TC homepage                                     e-mail@ berkeley