International
journals
F. Crupi,
Member, M. Alioto, J. Franco, P. Magnone,
M. Togo, N. Horiguchi, G. Groeseneken,
“Understanding the Basic Advantages of
Bulk FinFETs for Sub and NearThreshold
Logic from Device Measurements,” in
print on IEEE Trans. on Circuits and
Systems – part II
M.
Alioto, G. Palumbo, M. Pennisi, “A
Simple Circuit Approach to Reduce Delay
Variations in Domino Logic Gates,” in
print on IEEE Trans. on Circuits and
Systems – part I
F. Crupi,
M. Alioto, J. Franco, P. Magnone, B.
Kaczer, G. Groeseneken, J. Mitard, L.
Witters, T. Y. Hoffmann, “Buried Silicon
Germanium pMOSFETs: Experimental
Analysis in VLSI Logic Circuits under
Aggressive Voltage Scaling,” in print on
IEEE Trans. on VLSI Systems
D.
Baccarin, D. Esseni, M. Alioto, “Mixed
FBB/RBB: a Novel LowLeakage Technique
for FinFET Forced Stacks,” in print on
IEEE Trans. on VLSI Systems
F.
Frustaci, M. Alioto, P. Corsonello,
“TaperedVth Approach for
EnergyEfficient CMOS Buffers,” in print
on IEEE Trans. on Circuits and Systems –
part I
M.
Alioto, E. Consoli, G. Palumbo, “From
EnergyDelay Metrics to Constraints on
the Design of Digital Circuits,” in
print on International Journal of
Circuit Theory and Applications.
M.
Alioto, “UltraLow Power VLSI Circuit
Design Demystified and Explained: A
Tutorial,” in print on IEEE Trans. on
Circuits and Systems – part I (invited
extended paper).
M.
Alioto, ”Modeling Strategies of the
Input Admittance of RC Interconnects for
VLSI CAD Tools,” Microelectronics
Journal (Elsevier), vol. 42, no. 1, pp.
6373, Jan. 2011.
M.
Alioto, M. Poli, G. Palumbo, ”Optimized
Design of Parallel CarrySelect Adders,”
in print on Integration – the VLSI
Journal (Elsevier).
M.
Alioto, S. Badel, Y. Leblebici,
”Optimization of the Wire Grid Size for
Differential Routing: Analysis and
Impact on the PowerDelayArea
Tradeoff,” in print on Microelectronics
Journal (Elsevier).
P.
Magnone, F. Crupi, M. Alioto, B. Kaczer,
B. De Jaeger, ” Understanding the
Potential and the Limits of Germanium
pMOSFETs for VLSI Circuits from
Experimental Measurements,” in print on
IEEE Trans. on VLSI Systems
M.
Alioto, ”Comparative Evaluation of
Layout Density in 3T, 4T and MT FinFET
Standard Cells,” in print on IEEE Trans.
on VLSI Systems
M.
Alioto, E. Consoli, G. Palumbo,
“Analysis and Comparison in the
EnergyDelayArea Domain of Nanometer
CMOS FlipFlops: Part II – Results and
Figures of Merit,” in print on IEEE
Trans. on VLSI Systems
M.
Alioto, E. Consoli, G. Palumbo,
”Analysis and Comparison in the
EnergyDelayArea Domain of Nanometer
CMOS FlipFlops: Part I  Methodology
and Design Strategies,” in print on IEEE
Trans. on VLSI Systems
M.
Alioto, “Understanding DC Behavior of
Subthreshold CMOS Logic through
ClosedForm Analysis,” IEEE Trans. on
Circuits and Systems – part I, vol. 57,
no. 7, pp. 15971607, July 2010.
M.
Alioto, E. Consoli, G. Palumbo, “General
Strategies to Design Nanometer
FlipFlops in the EnergyDelay Space,”
IEEE Trans. on Circuits and Systems –
part I, vol. 57, no. 7, pp. 15831596,
July 2010.
M.
Alioto, E. Consoli, G. Palumbo,
“FlipFlop Energy/Performance versus
Clock Slope and Impact on the Clock
Network Design,” IEEE Trans. on Circuits
and Systems – part I, vol. 57, no. 6,
pp. 12731286, June 2010.
T.
Addabbo, M. Alioto, A. Fort, S. Rocchi,
V. Vignoli, “A variabilitytolerant
feedback technique for throughput
maximization of TRBGs with predefined
entropy,” in the Special Issue “Advances
in oscillator analysis and design” of
the Journal of Circuits, Systems, and
Computers, vol. 19, no. 4, pp. 879895,
2010.
M.
Alioto, G. Palumbo, M. Poli, “Simple and
Accurate Modeling of the Output
Transition Time in Nanometer CMOS
Gates,” in print on International
Journal of Circuit Theory and
Applications
M.
Alioto, L. Giancane, G. Scotti, A.
Trifiletti, “Leakage Power Analysis
Attacks: a Novel Class of Attacks to
Nanometer Cryptographic Circuits,” IEEE
Trans. on Circuits and Systems – part I,
vol. 57, no. 2, pp. 355367, Feb. 2010.
M.
Alioto, G. Palumbo, M. Pennisi,
“Understanding the Effect of Process
Variations on the Delay of Static and
Domino Logic,” IEEE Trans. on VLSI
Systems, vol. 18, no. 5, pp. 697710,
May 2010.
M.
Alioto, M. Poli, S. Rocchi, “A general
power model of Differential Power
Analysis attacks to static logic
circuits,” IEEE Trans. on VLSI Systems,
vol. 18, no. 5, pp. 711724, May 2010.
A.
Tajalli, M. Alioto, Y. Leblebici,
“Improving powerdelay performance of
ultralowpower subthreshold SCL circuits,”
IEEE Trans. on Circuits and Systems –
part II, vol. 56, no. 2, pp. 127131,
Feb. 2009.
M.
Alioto, M. Poli, S. Rocchi,
“Differential Power Analysis Attacks to
Precharged Busses: a General Analysis
for SymmetricKey Cryptographic
Algorithms,” IEEE Trans. on Dependable
and Secure Computing, vol. 7, no. 3, pp.
226239, JulySept. 2010.
M.
Agostinelli, M. Alioto, D. Esseni, L.
Selmi, "LeakageDelay Tradeoff in FinFET
Logic Circuits: a Comparative Analysis
with Bulk Technology," IEEE Trans. on
VLSI Systems, vol.18, no.2, pp. 232245,
Feb. 2010.
M.
Alioto, G. Palumbo, M. Poli, "Analysis
and Modeling of Energy Consumption in
RLC Tree Circuits," IEEE Trans. on VLSI
Systems, vol. 17, no. 2, pp. 278291,
Feb. 2009.
M.
Alioto, G. Palumbo, "PowerAware Design
of Nanometer MCML Tapered Buffers," IEEE
Trans. on Circuits and Systems – part II,
vol. 55, no. 1, pp. 1620, Jan. 2008.
M.
Alioto, G. Palumbo, "Very Fast Carry
Energy Efficient Computation based on
Mixed Dynamic/TransmissionGate Full
Adders," IEE Electronics letters, vol.
43, no. 13, pp. 707709, 21st June 2007.
M.
Alioto, L. Pancioni, S. Rocchi, V.
Vignoli, "PowerDelayAreaNoise Margin
Tradeoffs in PositiveFeedback
SourceCoupled Logic Gates," IEEE Trans.
on Circuits and Systems – part I, vol.
54, no. 9, pp. 19161928, Sept. 2007.
M.
Alioto, G. Palumbo, "InterconnectAware
Design of Fast Large FanIn CMOS
Multiplexers," IEEE Trans. on Circuits
and Systems – part II, vol. 54, no. 6,
pp. 484488, June 2007.
T.
Addabbo, M. Alioto, A. Fort, A. Pasini,
S.Rocchi, V. Vignoli, "A Class of
MaximumPeriod Nonlinear Congruential
Generators Derived From the Rényi
Chaotic Map", IEEE Trans. on Circuits
and Systems  part I, vol. 54, no. 4,
pp. 816828, April 2007.
M.
Alioto, G. Di Cataldo, G. Palumbo, "Mixed
Full Adder Topologies for
HighPerformance LowPower Arithmetic
Circuits," Microelectronics Journal,
vol. 38, no. 1, pp. 130139, Jan. 2007.
M.
Alioto, G. Palumbo, "Impact of Supply
Voltage Variations on Full Adder Delay:
Analysis and Comparison," IEEE Trans. on
VLSI Systems, vol. 14, no. 12, pp.
13221335, Dec. 2006.
M.
Alioto, G. Palumbo, "PowerAware Design
Techniques for Nanometer MOS
CurrentMode Logic Gates: a Design
Framework," IEEE Circuits and Systems
Magazine, vol. 6, no. 4, pp. 4059,
2006.
M.
Alioto, R. Mita, G. Palumbo, "Design of
HighSpeed PowerEfficient MOS
CurrentMode Logic Frequency Dividers",
IEEE Trans. on Circuits and Systems 
part II, vol. 53, no. 11, pp. 11651169,
Nov. 2006.
M.
Alioto, L. Pancioni, S. Rocchi, V.
Vignoli, "Exploiting Hysteresys in MCML
Circuits", IEEE Trans. on Circuits and
Systems  part II, vol. 53, no. 11, pp.
11701174, Nov. 2006.
T.
Addabbo, M. Alioto, A. Fort, S. Rocchi,
V. Vignoli, "The Digital Tent Map:
Performance Analysis and Optimized
Design as a Source of PseudoRandom
Bits," IEEE Transactions on
Instrumentation and Measurement, vol.
55, no. 5, pp. 14511458, Oct. 2006.
M.
Alioto, G. Palumbo, M. Poli, "Energy
Consumption in RC Tree Circuits", IEEE
Trans. on VLSI Systems, vol. 14, no. 5,
pp. 452461, May 2006.
M.
Alioto, A. D. Grasso, G. Palumbo,
"Design of Cascaded ECL Gates with a
Power Constraint", IEE Electronics
Letters, vol. 42, no. 4, pp. 211 212,
16th February 2006.
T.
Addabbo, M. Alioto, A. Fort, S. Rocchi,
V. Vignoli, "Low Hardware Complexity
PRBGs Based on a PiecewiseLinear
Chaotic Map," IEEE Transactions on CAS –
Part II, vol. 53, no. 5, pp. 329333,
May 2006.
T.
Addabbo, M. Alioto, A. Fort, S. Rocchi,
V. Vignoli, "A Feedback Strategy to
Improve the Entropy of a ChaosBased
Random Bit Generator," IEEE Transactions
on CAS – Part I, vol. 53, no. 2, pp.
326337, Feb. 2006.
M.
Alioto, G. Palumbo, "Modeling and Design
Considerations on CML Gates under
HighCurrent Effects," International
Journal of Circuit Theory and
Applications, vol. 33, no. 6, pp.
503518, Nov./Dec. 2005.
M.
Alioto, G. Palumbo, "Design strategies
of Cascaded CML Gates," IEEE
Transactions on CAS – part II, vol. 53,
no. 2, pp. 8589, Feb. 2006.
International
conference proceedings
J.
Richmond, M. John, L. Alarcon, W. Zhou,
W. Li, T.T. Liu, M. Alioto, S. R.
Sanders, J. M. Rabaey, “Active RFID: A
Perpetual Wireless Communications
Platform for Sensors,” in print on Proc.
of ESSCIRC 2012, Bordeaux (France),
Sept. 2012.
M.
Alioto, G. Palumbo, M. Pennisi, “A
Simple Keeper Topology to Reduce Delay
Variations in Nanometer Domino Logic,”
in Proc. of ISCAS 2012, pp. 15761579,
Seoul (Korea), May 2012.
F. Crupi,
P. Magnone, M. Alioto, J. Franco, G.
Groeseneken, “Early Assessment of
Emerging Technologies for VLSI Logic
Circuits from Experimental
Measurements,” in Proc. of ICSICT 2012 (invited).
E.
Consoli, M. Alioto, G. Palumbo, J.
Rabaey, “Conditional PushPull Pulsed
Latch with 726 fJ•ps Energy Delay
Product in 65nm CMOS,” in Proc. of ISSCC
2012, San Francisco (USA), Feb. 2012.
M.
Alioto, “'Impact of NMOS/PMOS Imbalance
in UltraLow Voltage CMOS Standard
Cells,” in Proc. of ECCTD 2011, pp.
557561, Linkoping (Sweden), Aug. 2011.
F.
Frustaci, P. Corsonello, M. Alioto,
“Optimization and Evaluation of TaperedVTH
Approach for EnergyEfficient CMOS
Buffers,” in print on Proc. of ECCTD
2011, Aug. 2011.
F. Crupi, M. Alioto, J. Franco, P.
Magnone, B. Kaczer, G. Groeseneken, J.
Mitard, L. Witters, T. Y. Hoffmann,
“Experimental Analysis of Buried SiGe
pMOSFETs from the Perspective of
Aggressive Voltage Scaling,” in print on
Proc. of ISCAS 2011, Rio de Janeiro
(Brazil), May 2011.
D. Baccarin, D. Esseni, M. Alioto, “A
Novel BackBiasing LowLeakage Technique
for FinFET Forced Stacks,” in print on
Proc. of ISCAS 2011, Rio de Janeiro
(Brazil), May 2011.
M. Alioto, E. Consoli, G. Palumbo, “DET
FF Topologies: A Detailed Investigation
in the EnergyDelayArea Domain,” in
print on Proc. of ISCAS 2011, Rio de
Janeiro (Brazil), May 2011.
F. Frustaci, P. Corsonello, M. Alioto,
“TaperedVTH CMOS Buffer Design for
Improved Energy Efficiency in Deep
Nanometer Technology,” in print on Proc.
of ISCAS 2011, Rio de Janeiro (Brazil),
May 2011.
M. Djukanovic, L. Giancane, G. Scotti,
A. Trifiletti, M. Alioto, “Leakage Power
Analysis Attacks: Effectiveness on DPA
Resistant Logic Styles under Process
Variations,” in print on Proc. of ISCAS
2011, Rio de Janeiro (Brazil), May 2011.
M. Alioto, “LowStandby Current 4T
FinFET Buffers: Analysis and Evaluation
below 45 nm,” in print on Proc. of ICM
2010, Cairo (Egypt), Dec. 2010.
M. Alioto, E. Consoli, G. Palumbo,
“Nanometer FlipFlops Design in the ED
Space,” in print on Proc. of ICM 2010,
Cairo (Egypt), Dec. 2010.
M. Alioto, E. Consoli, G. Palumbo,
“Physical Design Aware Selection of
EnergyEfficient and LowEnergy
Nanometer FlipFlops,” in print on Proc.
of ICM 2010, Cairo (Egypt), Dec. 2010.
J. Mitard, L. Witters, M. Garcia Bardon,
P. Christie, J. Franco, A. Mercha, P.
Magnone, M. Alioto, F. Crupi, L.A.
Ragnarsson, A. Hikavyy, B. Vincent, T.
Chiarella, R. Loo, J. Tseng, S.
Yamaguchi, S. Takeoka, W.W. Wang, P.
Absil, T. Hoffmann, “Subnm EOT
highmobility SiGe55% channel pFETs:
Delivering high performance at scaled
VDD,” accepted to IEEE IEDM 2010, San
Francisco (USA), Dec. 2010.
K. Agawa, M. Alioto, W. Zhou, T.T. Liu,
L. Alarcon, K. Hajkazemshirazi, M. John,
J. Richmond, W. Li, J. Rabaey, “Design
and Verification of an UltraLowPower
Active RFID Tag with Multiple Power
Domains,” in Proc. of SASIMI2010, Taipei
(Taiwan), Oct. 2010.
M. Alioto, E. Consoli, G. Palumbo,
“Physical Design Aware Comparison of
FlipFlops for HighSpeed
EnergyEfficient VLSI Circuits,” in
print on Proc. of PATMOS 2010, Grenoble
(France), Sept. 2010.
T. Addabbo, M. Alioto, A. Fort, S.
Rocchi, V. Vignoli, “A Scalable
LowEntropy Detector to Counteract the
Parameter Variability effects in TRBGs,”
in print on Proc. IMTC 2010, Austin
(USA), May 2010.
M. Merrett, Y. Wang, M. Alioto, M.
Zwolinski, “Design Metrics for RTL Level
Estimation of Delay Variability Due to
Intradie (Random) Variations,” in Proc.
of ISCAS 2010, pp. 24982501, Paris
(France), May 2010.
P. Magnone, F. Crupi, M. Alioto, B.
Kaczer, “Experimental Study of
LeakageDelay Tradeoff in Germanium
pMOSFETs for Logic Circuits,” in Proc.
of ISCAS 2010, pp. 16991702, Paris
(France), May 2010.
M. Alioto, “Analysis of Layout Density
in FinFET Standard Cells and Impact of
Fin Technology,” in Proc. of ISCAS 2010,
pp. 32043207, Paris (France), May 2010.
M. Alioto, P. Bennati, R. Giorgi,
“Exploiting Locality to Improve Leakage
Reduction in Embedded Drowsy ICaches at
Same Area/Speed,” in Proc. of ISCAS
2010, pp. 3740, Paris (France), May
2010.
M. Alioto, “ClosedForm Analysis of DC
Noise Immunity in Subthreshold CMOS
Logic Circuits,” in Proc. of ISCAS 2010,
pp. 14681471, Paris (France), May 2010.
M. Alioto, E. Consoli, G. Palumbo,
“Clock Distribution in Clock Domains
with DualEdgeTriggered FlipFlops to
improve EnergyEfficiency,” in Proc. of
ISCAS 2010, pp. 321324, Paris (France),
May 2010.
M. Alioto, E. Consoli, G. Palumbo,
“Optimum Clock Slope for FlipFlops
within a Clock Domain: Analysis and a
Case Study,” in Proc. of ICECS 2009, pp.
275278, Hammamet (Tunisia), Dec. 2009.
M. Alioto, G. Palumbo, M. Pennisi,
“Analysis of the Impact of Random
Process Variations in CMOS Tapered
Buffers,” in Proc. of ICECS 2009, pp.
5760, Hammamet (Tunisia), Dec. 2009.
M. Alioto, L. Giancane, G. Scotti, A.
Trifiletti, “Leakage Power Analysis
Attacks: Theoretical Analysis and Impact
of Variations,” in Proc. of ICECS 2009,
pp. 8588, Hammamet (Tunisia), Dec.
2009.
M. Alioto, E. Consoli, G. Palumbo,
“Dependence of Differential FlipFlops
Performance on Clock Slope and
Relaxation of Clock Network Design,” in
Proc. of ICM 2009, pp. 110113,
Marrakech (Morocco), Dec. 2009.
M. Alioto, M. Poli, S. Rocchi,
“LowOverhead Countermeasures to protect
Precharged Busses against Power
Analysis Attacks,” in Proc. of ICM 2009,
pp. 159162, Marrakech (Morocco), Dec.
2009.
M. Alioto, L. Giancane, G. Scotti, A.
Trifiletti, “Leakage Power Analysis
Attacks: WellDefined Procedure and
First Experimental Results,” in Proc. of
ICM 2009, pp. 4649, Marrakech
(Morocco), Dec. 2009.
M. Alioto, “Analysis and Evaluation of
Layout Density of FinFET Logic Gates,”
in Proc. of ICM 2009, pp. 106109,
Marrakech (Morocco), Dec. 2009.
M. Alioto, E. Consoli, G. Palumbo,
“Impact of Clock Slope on Energy/Delay
of Pulsed FlipFlops and Optimum Clock
Domain Design,” in Proc. of ECCTD 2009,
pp. 6164, Antalya (Turkey), Aug. 2009.
M. Alioto, E. Consoli, G. Palumbo, M.
Pennisi, “Correct Procedures to Evaluate
the Effect of Intradie Variations on the
Delay Variability of Digital Circuits,”
in Proc. of ECCTD 2009, pp. 779782,
Antalya (Turkey), Aug. 2009.
M. Alioto, E. Consoli, G. Palumbo,
“Metrics and Design Considerations on
the EnergyDelay Tradeoff of Digital
Circuits,” in Proc. of ISCAS 2009, pp.
31503153, Taipei (Taiwan), May 2009.
M. Alioto, Y. Leblebici, “Analysis and
Design of UltraLow Power Subthreshold
MCML Gates,” in Proc. of ISCAS 2009, pp.
25572560, Taipei (Taiwan), May 2009.
M. Alioto, “Understanding Loading
Effects of RC Uniform Interconnects,” in
Proc. of ISCAS 2009, pp. 22692272,
Taipei (Taiwan), May 2009.
M. Alioto, S. Badel, Y. Leblebici,
“Optimization of Wire Grid Size for
Differential Routing and Impact on the
PowerDelayArea Tradeoff,” in Proc. of
ISCAS 2009, pp. 12851288, Taipei
(Taiwan), May 2009.
M. Alioto, “CAD Models of the Input
Admittance of RC Wires: Comparison and
Selection Strategies,” in Proc. of ICM
2008, pp. 154157, Sharjah (United Arab
Emirates), Dec. 2008.
M. Alioto, M. Poli, G. Palumbo, “Compact
and Simple Output Transition Time Model
in Nanometer CMOS Gates,” in Proc. of
ICM 2008, pp. 235238, Sharjah (United
Arab Emirates), Dec. 2008.
M. Alioto, M. Poli, S. Rocchi, “Power
Analysis Attacks to Cryptographic
Circuits: a Comparative Analysis of DPA
and CPA,” in Proc. of ICM 2008, pp.
308311, Sharjah (United Arab Emirates),
Dec. 2008.
M. Alioto, Y. Leblebici, “Circuit
techniques to reduce the supply voltage
limit of subthreshold MCML circuits,” in
Proc. of VLSISoC 2008, pp. 239244,
Rhodes Island (Greece), Oct. 2008.
(INVITED)
Armin Tajalli, Massimo Alioto, Elizabeth
J. Brauer, Yusuf Leblebici, “Design of
High Performance Subthreshold
SourceCoupled Logic Circuits,” in Proc.
of PATMOS 2008, pp. 2130, Lisbon
(Portugal), Sep. 2008.
Matteo Agostinelli, Massimo Alioto,
David Esseni, Luca Selmi, “Design and
evaluation of mixed 3T4T FinFET stacks
for leakage reduction,” in Proc. of
PATMOS 2008, pp. 3141, Lisbon
(Portugal), Sep. 2008.
M. Alioto, G. Palumbo, M. Pennisi,
“Understanding the Effect of Intradie
Random Process Variations in Nanometer
Domino Logic,” in Proc. of PATMOS 2008,
pp. 136145, Lisbon (Portugal), Sep.
2008.
M. Alioto, G. Palumbo, M. Pennisi,
“Analysis of the impact of process
variations on static logic circuits
versus fanin,” in Proc. of ICECS 2008,
pp. 137140, Malta, Aug. 2008.
M. Alioto, G. Palumbo, M. Poli, “Energy
Evaluation in RLC Tree Circuits with
Exponential Input,” in Proc. of ICECS
2008, pp. 578581, Malta, Aug. 2008.
M. Alioto, L. Fondelli, S. Rocchi,
"Analysis and Performance Evaluation of
AreaEfficient True Random Bit
Generators on FPGAs", in Proc. of ISCAS
2008, pp. 15721575, Seattle (USA), May
2008.
A.
Tajalli, F. K. Gurkaynak, Y. Leblebici.
M. Alioto, E. J. Brauer, "Improving the
PowerDelay Product in SCL Circuits
Using Source Follower Output Stage", in
Proc. of ISCAS 2008, pp. 145148,
Seattle (USA), May 2008.
M. Alioto, G. Palumbo, M. Poli,
"Explicit Energy Evaluation in RLC Tree
Circuits with Ramp Inputs", in Proc. of
ISCAS 2008, pp. 28652868, Seattle
(USA), May 2008.
M. Alioto, G. Palumbo, "PowerDelay
Optimization in MCML Tapered Buffers",
in Proc. of ISCAS 2008, pp. 141144,
Seattle (USA), May 2008.
M. Alioto, M. Poli, S. Rocchi, "A
General Model for Differential Power
Analysis Attacks to Static Logic
Circuits", in Proc. of ISCAS 2008, pp.
33463349, Seattle (USA), May 2008.
M. Alioto, G. Palumbo, M. Poli,
"Efficient and Accurate Models of Output
Transition Time in CMOS Logic", Proc. of
ICECS 2007, pp. 12641267, Marrakech
(Morocco), Dec. 2007.
M. Alioto, "A Simple and Accurate Model
of Input capacitance for Power
Estimation in CMOS logic", Proc. of
ICECS 2007, pp. 431434, Marrakech
(Morocco), Dec. 2007.
M. Alioto, G. Palumbo, M. Poli, "Energy
Consumption in RLC Tree Circuits",
Proc. of ECCTD 2007, pp.
771774, Sevilla (Spain), Aug. 2007.
M. Alioto, G. Palumbo, "Very
HighSpeed Carry Computation based on
Mixed Dynamic/TransmissionGate Full
Adders",
Proc. of ECCTD 2007, pp.
799802, Sevilla (Spain), Aug. 2007.
M. Alioto, M. Poli, S. Rocchi, V.
Vignoli, "A
General Model of DPA Attacks to
Precharged Busses in SymmetricKey
Cryptographic Algorithms",
Proc. of ECCTD 2007, pp.
368371, Sevilla (Spain), Aug. 2007.
M. Agostinelli, M. Alioto, D. Esseni, L.
Selmi, "Trading off static power and
dynamic performance in CMOS digital
circuits: bulk versus double gate SOI
MOSFETs", Proc. of ESSDERC 2007,
pp. 191194, Munich (Germany), Sept.
2007.
M. Alioto, G. Palumbo, "Delay
Variability Due to Supply Variations in
TransmissionGate Full Adders",
Proc. of ISCAS 2007, pp.
37323735, New Orleans (USA), May 2007.
T. Addabbo, M. Alioto, A. Fort, S.
Rocchi, V. Vignoli, "MaximumPeriod
PRBGs Derived From A Piecewise Linear
OneDimensional Map",
Proc. of ISCAS 2007, pp. 693696,
New Orleans (USA), May 2007.
M. Alioto, G. Palumbo, "HighSpeed/LowPower
Mixed Full Adder Chains: Analysis and
Comparison versus Technology",
Proc. of ISCAS 2007, pp.
29983001, New Orleans (USA), May 2007.
M. Alioto, G. Palumbo, "Design of Fast
Large FanIn CMOS Multiplexers
Accounting for Interconnects", Proc.
of SCAS 2007, pp. 32553258, New
Orleans (USA), May 2007.
M. Alioto, M. Poli, S. Rocchi, V.
Vignoli, "Mixed Techniques to Protect
Precharged Busses against Differential
Power Analisys Attacks", Proc. of
ISCAS 2007, pp. 861864, New Orleans
(USA), May 2007.
T. Addabbo, M. Alioto, A. Fort, M.
Mugnaini, S. Rocchi, V. Vignoli,
"ImplementationEfficient MaximumPeriod
Nonlinear Congruential Generators",
Proc. of IMTC 2007, Warsaw
(Poland), May. 2007.
T. Addabbo, M. Alioto, A. Fort, S.
Rocchi, V. Vignoli, "Efficient
PostProcessing Module for a Chaosbased
Random Bit Generator", Proc. of
ICECS2006, pp. 12241227, Nice
(France), Dec. 2006.
M. Alioto, G. Palumbo, "Modeling of
Delay Variability due to Supply
Variations in PassTransistor and Static
Full Adders", Proc. of
ICECS2006, pp. 518521, Nice
(France), Dec. 2006.
M. Alioto, R. Mita, G. Palumbo, "A
Design Methodology for HighSpeed
LowPower MCML Frequency Dividers",
Proc. of ICECS2006, pp.
13081311, Nice (France), Dec. 2006.
T. Addabbo, M. Alioto, A. Fort, S.
Rocchi, V. Vignoli, "Entropy
Enhancement in a ChaosBased True Random
Bit Generators",
Proc. of NOLTA 2006, pp.
372378, Bologna (Italy), Sept. 2006.
M. Alioto, M. Poli, S. Rocchi, V.
Vignoli, "Techniques to Enhance the
Resistance of Precharged Busses to
Differential Power Analysis", Proc.
of PATMOS 2006, pp. 624633,
Montpellier (France), Sept. 2006.
M. Alioto, M. Poli, S. Rocchi, V.
Vignoli, "Power Modeling of Precharged
Address Bus and Application to Multibit
DPA Attacks to DES Algorithm", Proc.
of PATMOS 2006, pp. 593602,
Montpellier (France), Sept. 2006.
M. Alioto, A. D. Grasso, G. Palumbo,
"Design of Cascaded ECL Gates with a
Power Constraint", Proc. of PRIME
2006, pp. 233236, Otranto (Italy),
June 2006.
T. Addabbo, M. Alioto, A. Fort, S.
Rocchi, V. Vignoli, "A Technique to
Design High Entropy ChaosBased True
Random Bit Generators", Proc. of
ISCAS 2006, pp. 11831186, Kos
(Greece), May 2006.
M. Alioto, G. Palumbo, M. Poli,
"Efficient Output Transition Time
Modeling in CMOS Gates with
Ramp/Exponential Inputs", Proc. of
ISCAS 2006, pp. 51275130, Kos
(Greece), May 2006.
M. Alioto, L. Pancioni, S. Rocchi, V.
Vignoli, "Analysis and Design of MCML
Gates with Hysteresis", Proc. of
ISCAS 2006, pp. 12631266, Kos
(Greece), May 2006.
M. Alioto, G. Palumbo, "Nanometer MCML
Gates: Models and Design
Considerations", Proc. of
ISCAS 2006, pp. 38623865, Kos
(Greece), May 2006.
M.
Alioto, G. Palumbo, "Delay Uncertainty
Due to Supply Variations in Static and
Dynamic Full Adders", Proc. of ISCAS
2006, pp. 767770, Kos (Greece), May
2006.
T.
Addabbo, M. Alioto, A. Fort, S. Rocchi,
V. Vignoli, "UniformDistributed Noise
Generator Based on a Chaotic Circuit",
Proc of IMTC 2006, pp. 11561160,
Sorrento (Italy), April 2006.
