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International
journals
M. Alioto, G. Palumbo, "Design strategies of Cascaded CML
Gates," IEEE Transactions on CAS - part II, vol. 53, no. 2,
pp. 85-89, Feb. 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A
Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit
Generator," IEEE Transactions on CAS – Part I, vol. 53, no.
2, pp. 326-337, Feb. 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low
Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE
Transactions on CAS – Part II, vol. 53, no. 5, pp. 329-333, May 2006.
M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL
Gates with a Power Constraint", IEE Electronics Letters,
vol. 42, no. 4, pp. 211- 212, 16th February 2006.
M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC
Tree Circuits", IEEE Trans. on VLSI Systems, vol. 14, no. 5,
pp. 452-461, May 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The
Digital Tent Map: Performance Analysis and Optimized Design as a Source
of Pseudo-Random Bits," IEEE Transactions on Instrumentation and
Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006.
M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting
Hysteresys in MCML Circuits", IEEE Trans. on Circuits and Systems -
part II, vol.
53, no. 11, pp. 1170-1174, Nov. 2006.
M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed
Power-Efficient MOS Current-Mode Logic Frequency Dividers", IEEE
Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp.
1165-1169, Nov. 2006.
M. Alioto, G. Palumbo, "Power-Aware Design Techniques for
Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE
Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59, 2006.
M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations
on Full Adder Delay: Analysis and Comparison," IEEE Trans. on
VLSI Systems, vol. 14, no. 12, pp. 1322-1335, Dec. 2006.
M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder
Topologies for High-Performance Low-Power Arithmetic Circuits," Microelectronics
Journal, vol. 38, no. 1, pp. 130-139, Jan. 2007.
T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli,
"A Class of Maximum-Period Nonlinear Congruential Generators Derived
From the Rényi Chaotic Map", IEEE Trans. on Circuits and Systems
- part I, vol. 54, no. 4, pp. 816-828, April 2007.
M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast
Large Fan-In CMOS Multiplexers," accepted to IEEE Trans. on
Circuits and Systems – part II.
M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli,
"Power-Delay-Area-Noise Margin Trade-offs in Positive-Feedback
Source-Coupled Logic Gates," accepted to IEEE Trans. on Circuits
and Systems – part I.
M. Alioto, G. Palumbo, "Very Fast Carry Energy Efficient
Computation based on Mixed Dynamic/Transmission-Gate Full Adders,"
accepted to IEE Electronics letters.
M. Alioto, G. Palumbo, "Power-Aware Design of Nanometer MCML
Tapered Buffers," accepted to IEEE Trans. on Circuits and Systems
– part II.
M. Alioto, G. Palumbo, M. Poli, "Analysis and Modeling of
Energy Consumption in RLC Tree Circuits," IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291,
Feb. 2009.
M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay
Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk
Technology," in print on IEEE
Trans. on VLSI Systems.
M. Alioto, M. Poli, S. Rocchi, “Differential Power Analysis
Attacks to Precharged Busses: a General Analysis for Symmetric-Key
Cryptographic Algorithms,” in print on IEEE Trans. on Dependable and Secure Computing.
A. Tajalli, M. Alioto, Y. Leblebici, “Improving power-delay
performance of ultralow-power subthreshold SCL circuits,” IEEE Trans. on Circuits and Systems –
part II, vol. 56, no. 2, pp. 127-131, Feb. 2009.
M. Alioto, M. Poli, S. Rocchi, “A general power model of
Differential Power Analysis attacks to static logic circuits,” in print
on IEEE Trans. on VLSI Systems.
M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of
Process Variations on the Delay of Static and Domino Logic,” in print on IEEE Trans. on VLSI Systems
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power
Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic
Circuits,” in print on IEEE Trans.
on Circuits and Systems – part I
M. Alioto, G. Palumbo, M. Poli, “Simple and Accurate Modeling of
the Output Transition Time in Nanometer CMOS Gates,” in print on International Journal of Circuit
Theory and Applications
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A
variability-tolerant feedback technique for throughput maximization of
TRBGs with predefined entropy,” in print on the Special Issue “Advances
in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers
M. Alioto, E. Consoli, G. Palumbo, “Flip-Flop Energy/Performance
versus Clock Slope and Impact on the Clock Network Design,” in print on IEEE Trans. on Circuits and Systems –
part I
M. Alioto, E. Consoli, G. Palumbo, “General Strategies to Design
Nanometer Flip-Flops in the Energy-Delay Space,” in print on IEEE Trans. on Circuits and Systems –
part I
M. Alioto, “Understanding DC Behavior of
Subthreshold CMOS Logic through Closed-Form Analysis,” in print on IEEE Trans. on Circuits and Systems –
part I
M. Alioto, ”Comparative Evaluation of Layout Density in 3T, 4T and
MT FinFET Standard Cells,” in print on IEEE Trans. on VLSI Systems
M. Alioto, E. Consoli, G. Palumbo, ”Analysis and Comparison in the
Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I -
Methodology and Design Strategies,” in print on IEEE Trans. on VLSI Systems
M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison in the
Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II – Results
and Figures of Merit,” in print on IEEE
Trans. on VLSI Systems
International
conference proceedings
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli,
"Uniform-Distributed Noise Generator Based on a Chaotic
Circuit", Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April
2006.
M. Alioto, G. Palumbo, "Delay Uncertainty Due to Supply
Variations in Static and Dynamic Full Adders", Proc. of ISCAS 2006,
pp. 767-770, Kos (Greece), May 2006.
M. Alioto, G. Palumbo, "Nanometer MCML Gates: Models and
Design Considerations", Proc. of ISCAS 2006, pp. 3862-3865, Kos
(Greece), May 2006.
M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Analysis and
Design of MCML Gates with Hysteresis", Proc. of ISCAS 2006, pp.
1263-1266, Kos (Greece), May 2006.
M. Alioto, G. Palumbo, M. Poli, "Efficient Output Transition
Time Modeling in CMOS Gates with Ramp/Exponential Inputs", Proc. of
ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A
Technique to Design High Entropy Chaos-Based True Random Bit
Generators", Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May
2006.
M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL
Gates with a Power Constraint", Proc. of PRIME 2006, pp. 233-236,
Otranto (Italy), June 2006.
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Power Modeling of
Precharged Address Bus and Application to Multi-bit DPA Attacks to DES
Algorithm", Proc. of PATMOS 2006, pp. 593-602, Montpellier (France),
Sept. 2006.
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Techniques to
Enhance the Resistance of Precharged Busses to Differential Power
Analysis", Proc. of PATMOS 2006, pp. 624-633, Montpellier (France),
Sept. 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli,
"Entropy Enhancement in a Chaos-Based True Random Bit
Generators", Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy),
Sept. 2006.
M. Alioto, R. Mita, G. Palumbo, "A Design Methodology for
High-Speed Low-Power MCML Frequency Dividers", Proc. of ICECS2006,
pp. 1308-1311, Nice (France), Dec. 2006.
M. Alioto, G. Palumbo, "Modeling of Delay Variability due to
Supply Variations in Pass-Transistor and Static Full Adders", Proc.
of ICECS2006, pp. 518-521, Nice (France), Dec. 2006.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli,
"Efficient Post-Processing Module for a Chaos-based Random Bit
Generator", Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec.
2006.
T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V.
Vignoli, "Implementation-Efficient Maximum-Period Nonlinear
Congruential Generators", Proc. of IMTC 2007, Warsaw (Poland), May
2007.
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Mixed Techniques
to Protect Precharged Busses against Differential Power Analisys
Attacks", Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May
2007.
M. Alioto, G. Palumbo, "Design of Fast Large Fan-In CMOS
Multiplexers Accounting for Interconnects", Proc. of SCAS 2007, pp.
3255-3258, New Orleans (USA), May 2007.
M. Alioto, G. Palumbo, "High-Speed/Low-Power Mixed Full Adder
Chains: Analysis and Comparison versus Technology", Proc. of ISCAS
2007, pp. 2998-3001, New Orleans (USA), May 2007.
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli,
"Maximum-Period PRBGs Derived From A Piecewise Linear
One-Dimensional Map", Proc. of ISCAS 2007, pp. 693-696, New Orleans
(USA), May 2007.
M. Alioto, G. Palumbo, "Delay Variability Due to Supply
Variations in Transmission-Gate Full Adders", Proc. of ISCAS 2007,
pp. 3732-3735, New Orleans (USA), May 2007.
M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Trading off
static power and dynamic performance in CMOS digital circuits: bulk
versus double gate SOI MOSFETs", Proc. of ESSDERC 2007, pp. 191-194,
Munich (Germany), Sept. 2007.
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "A General Model
of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic
Algorithms", Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug.
2007.
M. Alioto, G. Palumbo, "Very High-Speed Carry Computation
based on Mixed Dynamic/Transmission-Gate Full Adders", Proc. of
ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007.
M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RLC
Tree Circuits", Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain),
Aug. 2007.
M. Alioto, "A Simple and Accurate Model of Input capacitance
for Power Estimation in CMOS logic", Proc. of ICECS 2007, pp.
431-434, Marrakech (Morocco), Dec. 2007.
M. Alioto, G. Palumbo, M. Poli, "Efficient and Accurate
Models of Output Transition Time in CMOS Logic", Proc. of ICECS
2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007.
M. Alioto, M. Poli, S. Rocchi, "A General Model for
Differential Power Analysis Attacks to Static Logic Circuits", in
Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008.
M. Alioto, G. Palumbo, "Power-Delay Optimization in MCML
Tapered Buffers", in Proc. of ISCAS 2008, pp. 141-144, Seattle
(USA), May 2008.
M. Alioto, G. Palumbo, M. Poli, "Explicit Energy Evaluation
in RLC Tree Circuits with Ramp Inputs", in Proc. of ISCAS 2008, pp.
2865-2868, Seattle (USA), May 2008.
A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J.
Brauer, "Improving the Power-Delay Product in SCL Circuits Using
Source Follower Output Stage", in Proc. of ISCAS 2008, pp. 145-148,
Seattle (USA), May 2008.
M. Alioto, L. Fondelli, S. Rocchi, "Analysis and Performance
Evaluation of Area-Efficient True Random Bit Generators on FPGAs",
in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008.
M. Alioto, G. Palumbo, M. Poli, “Energy Evaluation in RLC Tree
Circuits with Exponential Input,” accepted to ICECS 2008, Malta, Aug.
2008.
M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the impact of
process variations on static logic circuits versus fan-in,” accepted to
ICECS 2008, Malta, Aug. 2008.
M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of
Intradie Random Process Variations in Nanometer Domino Logic,” in Proc.
of PATMOS 2008, pp. 136-145, Lisbon (Portugal), Sep. 2008.
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi,
“Design and evaluation of mixed 3T-4T FinFET stacks for leakage
reduction,” in Proc. of PATMOS 2008, pp. 31-41, Lisbon (Portugal), Sep.
2008.
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici,
“Design of High Performance Subthreshold Source-Coupled Logic Circuits,”
in Proc. of PATMOS 2008, pp. 21-30, Lisbon (Portugal), Sep. 2008.
M. Alioto, Y. Leblebici “Circuit techniques to reduce the supply
voltage limit of subthreshold MCML circuits,” in Proc. of VLSI-SoC 2008,
pp. 239-244, Rhodes Island (Greece), Oct. 2008. (INVITED)
M. Alioto, M. Poli, S. Rocchi, “Power Analysis Attacks to
Cryptographic Circuits: a Comparative Analysis of DPA and CPA,” in Proc.
of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008.
M. Alioto, M. Poli, G. Palumbo, “Compact and Simple Output
Transition Time Model in Nanometer CMOS Gates,” in Proc. of ICM 2008, pp.
235-238, Sharjah (United Arab Emirates), Dec. 2008.
M. Alioto, “CAD Models of the Input Admittance of RC Wires:
Comparison and Selection Strategies,” in Proc. of ICM 2008, pp. 154-157,
Sharjah (United Arab Emirates), Dec. 2008.
M. Alioto, S. Badel, Y. Leblebici, “Optimization of Wire Grid Size
for Differential Routing and Impact on the Power-Delay-Area Tradeoff,” in
Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009.
M. Alioto, “Understanding Loading Effects of RC Uniform
Interconnects,” in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan),
May 2009.
M. Alioto, Y. Leblebici, “Analysis and Design of Ultra-Low Power
Subthreshold MCML Gates,” in Proc. of ISCAS 2009, pp. 2557-2560, Taipei
(Taiwan), May 2009.
M. Alioto, E. Consoli, G. Palumbo, “Metrics and Design
Considerations on the Energy-Delay Tradeoff of Digital Circuits,” in
Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009.
M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, “Correct Procedures
to Evaluate the Effect of Intradie Variations on the Delay Variability of
Digital Circuits,” accepted to ECCTD 2009, Antalya (Turkey), Aug. 2009.
M. Alioto, E. Consoli, G. Palumbo, “Impact of Clock Slope on
Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,”
accepted to ECCTD 2009, Antalya (Turkey), Aug. 2009.
M. Alioto, “Analysis and Evaluation of Layout Density of FinFET
Logic Gates,” in Proc. of ICM 2009, pp. 106-109, Marrakech (Morocco), Dec. 2009.
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power
Analysis Attacks: Well-Defined Procedure and First Experimental Results,”
in Proc. of ICM 2009, pp. 46-49, Marrakech (Morocco), Dec. 2009.
M. Alioto, M. Poli, S. Rocchi, “Low-Overhead Countermeasures to
protect Pre-charged Busses against Power Analysis Attacks,” in Proc. of
ICM 2009, pp. 159-162, Marrakech (Morocco), Dec. 2009.
M. Alioto, E. Consoli, G. Palumbo, “Dependence of Differential
Flip-Flops Performance on Clock Slope and Relaxation of Clock Network
Design,” in Proc. of ICM 2009, pp. 110-113, Marrakech (Morocco), Dec.
2009.
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power
Analysis Attacks: Theoretical Analysis and Impact of Variations,” in
Proc. of ICECS 2009, pp. 85-88, Hammamet (Tunisia), Dec. 2009.
M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the Impact of
Random Process Variations in CMOS Tapered Buffers,” in Proc. of ICECS
2009, pp. 57-60, Hammamet (Tunisia), Dec. 2009.
M. Alioto, E. Consoli, G. Palumbo, “Optimum Clock Slope for
Flip-Flops within a Clock Domain: Analysis and a Case Study,” in Proc.
ICECS 2009, pp. 275-278, Hammamet (Tunisia), Dec. 2009.
M. Alioto, E. Consoli, G. Palumbo, “Clock Distribution in Clock
Domains with Dual-Edge-Triggered Flip-Flops to improve
Energy-Efficiency,” in print on Proc. ISCAS 2010, Paris (France), May
2010.
M. Alioto, “Closed-Form Analysis of DC Noise Immunity in
Subthreshold CMOS Logic Circuits,” in print on Proc. ISCAS 2010, Paris
(France), May 2010.
M. Alioto, P. Bennati, R. Giorgi, “Exploiting Locality to Improve
Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed,” in
print on Proc. ISCAS 2010, Paris (France), May 2010.
M. Alioto, “Analysis of Layout Density in FinFET Standard Cells
and Impact of Fin Technology,” in print on Proc. ISCAS 2010, Paris
(France), May 2010.
P. Magnone, F. Crupi, M. Alioto, B. Kaczer, “Experimental Study of
Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits,” in
print on Proc. ISCAS 2010, Paris (France), May 2010.
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